JPH08130534A - Data transmission adaptive system and data transmitter provided with the system - Google Patents

Abstract

PURPOSE: To attain a data transmission adaptive system and a data transmitter provided with the adaptive system which can cope with high speed data transmission without being affected by a data transmitter or a transmission line on an opposite party side. CONSTITUTION: An oscillator 12 generates clocks. A receiver 10 receives data sent with a 1st clock from the oscillator 12 as a synchronizing clock. A difference detecting circuit 14 inputs the 1st clock and an n-fold clock obtained by multiplying the 1st clock by (n) and detects the delay or advance of the sent data by the use of the 1st clock and the n-fold clock. An adaptive circuit 16 inputs the 1st clock and the n-fold clock, inputs the delay or advance of data detected by a difference detecting circuit 14, generates a 2nd clock obtained by advancing or delaying the 1st clock within an n-fold frequency range based upon these inputted values, and sends the 2nd clock to the data transmitting side as a synchronizing clock.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission device, and more particularly to data transmission adaptation of a data transmission device for exchanging data at high speed between the devices.

[0002]

2. Description of the Related Art A data transmission apparatus synchronizes with another data transmission apparatus connected via, for example, an analog line network or a digital line network at a relatively high speed by synchronizing with each other by a clock from a common clock source. While transmitting and receiving data. Specifically, the data and the clock are transmitted separately, and the data transmission is performed in synchronization with the clock from one of the data transmission devices. For example, CC
V. ITT Recommendation 24 and X. 21 shows the definition of the mutual circuit between the data line terminators in the analog network and the digital network, respectively. Normally, the physical condition, the electrical condition and the logical condition of the terminal interface are determined according to this standard. .

FIG. 4 shows an example of connection in data transmission of a data transmission device in such a conventional technique.
In the figure, a case is shown in which the data transmission device 4 and the data transmission device 2 are connected via the transmission path 100, and the data transmission device 2 performs data transmission in synchronization with the clock from the data transmission device 4. That is, the clock output from the oscillator 12 of the data transmission device 4 is supplied to the receiver 10 of the device 4 and the transmitter of the data transmission device 2 so that the transmission side and the reception side are synchronized with each other. Data is received by the data transmission device 4. When data transmission is performed in this way, the timing of data transmission and reception is determined by the synchronous clock, so the synchronous clock is a very important factor in data transmission between terminals.

On the other hand, in recent years, the amount of information in data transmission has dramatically increased, and there has been a desire for higher speed data transmission.
The data transmission device has also been improved to meet this demand.

[0005]

However, conventionally,
Although line drivers and receivers have been speeded up in order to speed up data transmission, no consideration has been given to the delay of the synchronous clock due to the speeding up. Generally, the data transmission device is connected to an unspecified partner. Therefore, the clock delay differs depending on the line state and the connection partner at that time, and this cannot be specified in advance.

Therefore, there is no problem if the speed is high enough to ignore the delay of the data with respect to the clock even if the line condition and the condition of the other party of the connection are taken into consideration. However, the data transmission speed is further increased to transfer the data. When the reception timing is affected, the phase difference between the data and the clock becomes so large that it cannot be ignored, and there is a problem that data transmission becomes substantially impossible.

That is, in the example shown in FIG. 4, since the data transmission device 2 is connected to the network, the data transmission devices 2 and 4 must be synchronized with the clock source of the network output from this device 2. . However, since a delay in the data transmission device 2 and a delay in the transmission line 100 (variation A to variation C) occur, a deviation occurs between the clock supplied to the receiver 10 of the data transmission device 4 and the received data. .

FIG. 6 is a time chart showing this situation. The clock a is a clock supplied from the oscillator 12, and the receiver 10 receives the clock a with almost no delay. On the other hand, the data transmitted from the transmitter 20 due to the fluctuations A to C is delayed by the delay time t ₁ and received by the receiver. Therefore, when the delay time t ₁ further moves to the range delayed from the time T ₁ , the receiver 10 cannot sample the data from the transmitter 20 with the clock of the oscillator 12.

In order to avoid such a problem, it is conceivable to install an oscillator for outputting a clock also in the data transmission device 2 to perform data transmission. However, the separately provided clock source is not synchronized with the clock of the network on the data transmission device 4 side if the phase is different. Therefore, it is very difficult to accurately receive data even if a buffer such as a FIFO is provided in the data transmission device 4 on the receiving side to perform clock transfer processing. This is the same as the case where the data transmission device 2 does not directly supply the clock to the data transmission device 4 but the data transmission device 4 uses a PLL (Phase Locked Loop) or the like to reproduce the clock from the received data.

Further, as described above, the values of the fluctuations A to C shown in FIG. 4 change each time the partner for data transmission changes. Therefore, there is a need for a delay measure that can be flexibly adapted in data transmission with different data transmission devices.

The present invention solves the above-mentioned drawbacks of the prior art, and a data transmission adaptation method capable of supporting high-speed data transmission without being affected by the data transmission device or transmission path of the other side, and a data transmission system including the same. An object is to provide a transmission device.

[0012]

In order to solve the above-mentioned problems, the present invention solves the above-mentioned problems by an oscillator 12 for generating a clock and a receiver for receiving data sent from the oscillator 12 as a synchronous clock. The first clock and the n-fold clock obtained by multiplying the first clock by n times are input from the instrument 10 and the oscillator 12, and the delay or advance of the transmitted data is detected by the first clock and the n-fold clock. And the difference detection circuit 14 that receives the first clock and the n-fold clock from the oscillator 12
The delay or advance of the detected data is input, the second clock is generated by advancing or delaying the first clock in the frequency range multiplied by n by these values, and the second clock is used as the synchronous clock. And the adaptation circuit 16 for sending to the transmitting side of the.

[0013]

According to the present invention, the data transmitted by the data transmission device 1 receives the data transmitted from the data transmission device 2 by using the first clock generated inside the data transmission device 1 as the synchronous clock. In the transmission adaptation method, the data transmission device 1 receives the data sent from the data transmission device 2 by using the first clock as a synchronous clock, and delays or advances this data from the first clock and the received data. The second clock that is detected and adapted to the first clock according to the detected value is sent to the data transmission device 2 as a synchronous clock.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a data transmission apparatus having a data transmission adaptation system according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a system configuration diagram showing an embodiment of a data transmission apparatus provided with a data transmission adaptation system according to the present invention. Data transmitted from the data transmission apparatus 2 by a synchronous clock from the data transmission apparatus 1 is It is received by the data transmission device 1. That is, in FIG. 1, the data transmission device 1 is a data transmission device having a data transmission adaptation function, and is connected to the normal data transmission device 2 described in FIG.

The data transmission device 1 comprises a receiver 10, an oscillator 12, a difference detector 14 and an adaptation circuit 16. The oscillator 12 is an oscillator that generates and outputs a clock. From this, an original clock (hereinafter referred to as a first clock) and an n-fold clock (n * CLK) having a frequency n times that of the original clock are transmitted. . The oscillator 12 is connected to the receiver 10, the difference detection circuit 14, and the adaptation circuit 16, and supplies the generated clock to them.

The receiver 10 is connected to the transmission line 100 and receives data sent from another data transmission device via the transmission line 100. That is, the receiver 10 receives the data accurately by sampling the data sent from the transmitter 20 of the data transmission device 2 with the first clock supplied from the oscillator 12.

The difference detection circuit 14 includes a first oscillator from the oscillator 12.
And the n-fold clock are input, and the delay or advance of the transmitted data is detected by the first clock and the n-fold clock. The difference detection circuit 14 is an adaptation circuit 1.
6 and outputs the detected delay or advance information to the circuit 16.

The adaptation circuit 16 inputs the first clock and the n-fold clock from the oscillator 12, and also inputs the delay or advance information of the data detected by the difference detection circuit 14. Then, the adaptation circuit 16 generates a second clock by advancing or delaying the first clock within a frequency range multiplied by n by these values, and uses this second clock as a synchronization clock on the data transmission side. It is sent to the data transmission device 2. This second clock substantially becomes the synchronous clock on the interface.

In FIG. 1, the variation A is the data transmission device 2
This is a value indicating the delay peculiar to the device, and this value also changes if the other party for data transmission changes. Further, the fluctuations B and C are peculiar to the transmission path to be used, and their values fluctuate depending on the distance and the type. Therefore, in the data transmission device 1, the difference detection circuit 14 detects the phase difference from the first clock from the data sent from the data transmission device 2, and the adaptation circuit 1
6 corrects the clock phase.

When the phase of the clock is corrected, even if the phase of the received data deviates by one clock (one element length) or more, it is necessary to adapt the data and the clock so that a sufficient margin can be obtained. That is, it must be taken into consideration so that even if the delay becomes large and the data phase shifts by one clock or more and the data advances, it can be adapted. Although a delay actually occurs due to the fluctuation B / C of the transmission path 100 and the fluctuation A of the data transmission device 2, it is important to recognize that the delay is a lead in order to reliably control the phase state of the clock. In the present embodiment, not only the delay but also the advance can be detected because in consideration of this point, the phase of the clock can be surely corrected.

FIG. 5 is a time chart showing this situation. The clock a is a clock supplied from the oscillator 12, and the receiver 10 receives this clock with almost no delay. On the other hand, due to the fluctuations A to C, the transmitter 20
The transmission data from is received by the receiver 10 after being delayed by the delay time t ₂ . Therefore, the phase detection comes to the timing shown in FIG. 6, and the actual data can be accurately received by the clock b whose phase is aligned. Even in the range of T ₂ when the received data is further delayed, the clock b is detected by the phase detection.
To adapt. In addition, the delay is the advance of the next timing, and the maximum delay is the minimum advance, and it is called adaptation.

FIG. 2 is a circuit diagram of the difference detection circuit 14 and the adaptation circuit 16 which are the main parts of this embodiment. In the present embodiment, the phase adjustment is performed with a clock that is n times the original clock that is the first clock. This n-fold clock has a higher frequency, but the higher the frequency, the higher the cost of the circuit and the larger the hardware scale.

For this reason, the embodiment of FIG. 2 shows an example in which the n-fold clock is the 16-fold clock, but the present invention is not limited to the 16-fold clock, as a matter of course. In addition,
When the value of n changes, the number of digits of the up / down counter 162 of the adaptation circuit 16 and the shift register 164.
The number of stages 164 and the 16 → 1 selector 168 change according to the value.

The difference detection circuit 14 includes two D flip-flops 142 and 144, an exclusive OR gate 146, an inverter 148, and two AND gates 150 and 152.
It consists of. Two D flip-flops 14
The 2 · 144 and the exclusive OR gate 146 are circuits that extract a change point of the data sent from the data transmission device 2. The inverter 148 and the AND gates 150 and 152 are circuits that detect the phase difference between the input data and the clock from this change point.

That is, the D flip-flop 142 is
By latching the input data a with an n-fold clock, the data b whose timing is delayed by 1/16 of the original clock e is sent to the input side of the D flip-flop 144 and the exclusive OR gate 146. The D flip-flop 144 sends the input data b to the input side of the exclusive OR gate 146 by latching the input data b with an n-fold clock and similarly delaying the 1/16 timing. By inputting these data, the exclusive OR gate 146 extracts the change point of the transmitted data.

The data d from which the change point is extracted is logically ANDed with the original clock e by the AND gate 15 and the clock f obtained by inverting the original clock e by the inverter 148 and the AND gate 152. As a result, when the received data is delayed, the pulse g which detects the phase difference from the original clock e, and when the received data is advanced, the pulse h which detects the phase difference from the original clock e. Is output to the adaptation circuit 16.

The adaptation circuit 16 is composed of an up / down counter 162, shift registers 164 and 166, a 16 → 1 selector 168, and a D flip-flop 170. The up / down counter 162 uses the pulse g
Is input, the count-down value is input, and when pulse h is input, the count-up value is input.
It is a counter that outputs to 68.

That is, in the counter 162, among the input terminals 0 to 3 for determining the reference value for counting, the input terminals 0 to 2 are connected to the "L" level and the input terminal 3 is connected to the "H" level. Here, since the input terminal 0 is the LSB and the input terminal 3 is the MSB, the reference value is “0110” in binary and “6” in decimal. Therefore, in the initial state, "0110" indicating "6" is output from the output terminals 0 to 3, and the output value changes by inputting the pulse g or h. In this way, the up / down counter 1
Reference numeral 62 holds the information on the advance and the delay from the difference detection circuit 14.
Output.

Output terminal 0 of up / down counter 162
3 to 3 are connected to the input terminals A to D of the 16 → 1 selector 168, respectively. The 16 → 1 selector 168 also
The output terminals 0 to 7 from the shift register 164 and the output terminals 8 to 15 from the shift register 166 are connected to the input terminals 0 to 15, respectively. The 16 → 1 selector 168 receives the signals input to the input terminals 0 to 15 according to the values input to the input terminals A to D (the shift register SR in FIG. 3).
(Signals 0 to 15) are selected.

That is, when the up / down counter 162 indicates "5", the output terminals 0, 1, 2, and 3 are "1", "0", "1", and "0" (binary number "010").
1 ″), the 16 → 1 selector 168 outputs the input from the input terminal 7 as a signal j from the output terminal O. When the value of the counter 162 is “−1” by the difference detection circuit 14, the up / down counter is turned on. 162 output terminals 0, 1,
2 and 3 become "4" of "0", "1", "1", and "0", respectively, and the 16 → 1 selector 168 outputs the input of the input terminal 6 from the output terminal O as the signal j. The signal j is input to the D flip-flop 170, which outputs the synchronous clock i in which the data delay is adapted. This operation continues until there is no delay, and the same processing is performed in the case of the reverse operation of advance.

FIG. 3 is a timing chart showing each waveform in the circuit of FIG. The original clock is input to the shift registers 164 and 166, and the waveforms output from these shift registers 164 and 166 are shown in the shift registers SR0 to SR15. Shift registers 164, 16
Since the clock of No. 6 is 16 times here, the original clock has a waveform shifted in phase by one clock of the n times clock (n * CLK) which is 16 times. As described above, these waveforms are input to the 16 → 1 selector 168, and only one of them is selected. This signal becomes the signal j.

The signal a has a waveform delayed by one clock of the n-fold clock each time it passes through the D flip-flops 142 and 144 at the n-fold clock. This delayed waveform b
When the exclusive OR of the signals of c and c is calculated, the change point of the signal is output as a pulse d. This is compared with the original clock to detect the delayed pulse g or the advanced pulse h.
The counter 162 is moved up / down by this delay or advance, a counter value for controlling the 16 → 1 selector 168 is obtained, and the synchronous clock is adapted by changing this counter value according to the delay / advance of data. .

The reference value of the up / down counter 162 is "6" as described above. Therefore, if there is no delay or advance of data, the synchronous clock j becomes the same clock as the original clock. Further, when the data is delayed, the synchronous clock needs to be advanced from the original clock. Therefore, in this embodiment, the clock j is input to the D flip-flop, and the clock i, which is the inverted output of the waveform delayed by one clock of the n-fold clock, is output as the second clock that is the network synchronization clock. .

The present invention is not particularly limited to this embodiment. That is, for example, the transmission line 100 is illustrated as being wired in the present embodiment, but the present invention can be applied even if it is wireless.

[0036]

As described above, according to the present invention, a synchronous clock is supplied from one data transmission device and data delayed from the other data transmission device is received. It is possible to adapt and reliably receive the transmitted data. Further, in the present invention, the adaptation works even when the device on the data transmission side is changed or the transmission path is changed. Furthermore, it can be applied to multi-point connections even if the phases are different when receiving from multiple stations. The most important feature of the present invention is that the transmission side of the data is adapted to the output phase of the oscillator synchronized with the network, so that the transmission side performs advanced phase control such as flip-flop and clock phase control (PLL). Data can be sent directly to the network in synchronization with the synchronous clock.

[Brief description of drawings]

FIG. 1 is a system configuration diagram showing an embodiment of a data transmission adaptation system according to the present invention.

FIG. 2 is a circuit diagram showing a main part of a data transmission adaptation method according to the present invention.

FIG. 3 is a timing chart showing each waveform of the circuit diagram shown in FIG.

FIG. 4 is a system configuration diagram of a data transmission system in a conventional technique.

FIG. 5 is a timing chart showing that a phase difference occurs between the synchronous clock and data.

FIG. 6 is a time chart showing that a shift occurs between the clock supplied to the receiver 10 and the received data.

[Explanation of symbols]

 1 data transmission device equipped with data transmission adaptation system 2 data transmission device 10 receiver 12 oscillator 14 difference detection circuit 16 adaptation circuit 20 transmitter 142 D flip-flop 144 D flip-flop 146 exclusive OR gate 148 inverter 150 AND Gate 152 AND gate 162 Up-down counter 164 Shift register 166 Shift register 168 16 → 1 selector 170 D flip-flop

Claims (2)

[Claims] 1. A data transmission device in which a first clock generated inside the data transmission device (1) is used as a synchronous clock.
In the data transmission adaptation method in the data transmission device in which the data transmission device (1) receives the data sent from (2), the data transmission device (1) uses the first clock as a synchronization clock. 2) The data sent from is received, and the delay or advance of this data is detected from the first clock and the received data, and the first clock is adapted according to the detected value. Data transmission device using second clock as synchronization clock
A data transmission adaptation method characterized by sending to (2). 2. An oscillator (12) for generating a clock, a receiver (10) for receiving data sent from the oscillator (12) as a synchronous clock, and the oscillator (12) for receiving the data. A difference detection circuit (14) for inputting a first clock and an n-fold clock obtained by multiplying the first clock by n, and detecting the delay or advance of the transmitted data with the first clock and the n-fold clock. ), The first clock and the n-fold clock are input from the oscillator (12), and the delay or advance of the detected data is input from the difference detection circuit (14). And an adaptation circuit (16) for generating a second clock that advances or delays the first clock within a range and sending the second clock as a synchronization clock to the data transmission side. Data transmission Location.