JPH01309447A - Single line synchronizing type communication system - Google Patents

Abstract

PURPOSE:To build up a data transmission system with a single line and low current consumption at a high speed without using a complicated modulator- demodulator circuit by arranging a synchronizing clock pulse and a data pulse alternately in a data format. CONSTITUTION:A 1-bit data is placed between a synchronizing pulse and that of the preceding bit, and when the data is logical '1', a data pulse is outputted and when the data is logical '0', no data pulse is outputted. With a signal 1a given at logical 'L', the transmission data is separated into a clock pulse and a data pulse by applying sampling to the data. In the presence of a data pulse, since a signal RX is set in the inverse of signal 1a at logical 'H', a Q output of a D-F/F5 goes to 'H' and in the absence of a data pulse, since no change arises in a signal RX12 for the inverse of signal 1a at logical 'H', then an output RXD of the D-F/F5 goes to logical L.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a single-wire synchronous communication system in a digital data communication system.

[Summary of the invention]

The purpose of the present invention is to perform data communication between asynchronous devices at low current consumption and high speed using a single wire. By providing a data transfer modem with a transfer pattern format that determines data in a This has been made possible.

[Conventional technology]

Conventionally, digital communication systems are divided into synchronous and asynchronous systems, and in single-wire communication in particular, the start-stop synchronous system, which is an asynchronous system, is widely used. On the other hand, in synchronous communication, between the transmitting and receiving stations,
A method of adding a clock signal to other than the data signal line, and
A transmission method using M or AM modulation is used.

[Problem to be solved by the invention]

Conventional single-wire data communication requires a clock that is at least 16 times the communication rate for asynchronous communication, which limits its use in systems that require low current consumption and high-speed transfer.

Furthermore, synchronous communication using modulation methods such as AM and FM requires complicated circuits, which limits its use in systems with low current consumption, such as small battery-powered portable devices.

Furthermore, providing a line for a synchronous clock separately from a data line also imposes limitations on the system in which it can be used.

[Failure to solve the problem]

In order to solve the above problems, the present invention makes it possible to perform synchronous communication over a single wire by arranging synchronization pulses and data pulses alternately in the data formant.

In the data format according to this invention, on the sending side,
A clock that is twice the communication rate is used as a carrier wave, and the receiving side uses a clock that is four times the communication rate to enable transmission and reception at any timing.

[Effect]

As mentioned above, in the communication method according to the present invention, a single signal line includes a synchronization clock and data, and each device can communicate by providing a clock that is four times the communication rate. .

Further, since a modem implementing the method according to the present invention does not require complicated modulation/demodulation, it can be constructed with a simple circuit.

This will expand the scope of its use in systems that require low current consumption and high-speed data transfer using a single wire, such as small battery-powered portable data collection devices.

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

1 (al to 1 Fdi) are data formants of the communication system of the present invention. +8+ in FIG. 1 represents the arrangement of the synchronizing pulse 16 and the data pulse 17, and the 1-bit section. One bit of data is located between the synchronizing pulse and the next bit's synchronizing pulse, and when it is "1",
It is assumed that data pulses are output and no data pulses are output during rOJO. The communication rate is the same as the frequency of the synchronization pulse.

Figure 1 (bl - Figure 1 Fdl are examples of communication patterns. In Figure 1 +8+, IQ, L L O, I J data, in Figure 1 (C1, "Sail 0.0, 0. OJ In FIG. 1 +8+, the data of II, L L 1. I J are expressed by the presence or absence of the data pulse 17, respectively.

FIGS. 2 and 3 show examples of circuits for implementing the modem of the present invention. FIG. 2 shows an example of a circuit on the receiving side. The signal RX in the above format is connected to the clock terminal of DF/Fl, and at the rising edge of RX, the output of DF/Fl becomes rHJ. This output is sampled by the D-F/F2 at the rising edge of the clock signal 40, which is four times the communication clock. The mouth output of D-F/F2 is D-F/F
3, sampled at the falling edge of signal 4C',
The output of DF/F3 is sampled by DF/F4 at the falling edge of signal 4CK.

The output of the D-F/F4 is a reception synchronization clock RX. The output of DF/F4 and the ζ output of DF/F3 are connected to the reset of DF/Fl via NAND gate 2. The output of D-F/Fl is sampled at the rising edge of RX at D-F/P5 to output received data RXD. D-F/F5 is D-F/Fl
It is reset by the oral output.

FIG. 3 is an example of a circuit on the transmitting side. Divide the clock signal 2CK, which is twice the communication clock, by z using D-F/F6 to obtain D-F/
The output of F6 is sampled by DP/F7 at the falling edge of 2CK. The mouth output of D-F/F7 is further D-
It is sampled at the falling edge of 2CK by F/F8.

The output of the D-F/F6 is a transmission clock TXC, and the transmission data TXD is output in synchronization with this signal. AND gate 14 connects TXD and D-F/F6
, the output of D-F/F1, and the output of D-F/F8 are input, and the AND gate 13 is connected to D-F/F.
The mouth output of 6 and the mouth output of DF/F7 are input.

The OR gate 15 ORs the outputs of the AND gates 3 and 14 and outputs a transmission pattern TX according to the data format.

Next, the operation will be explained in detail according to the timing diagrams of FIGS. 4 and 5. FIG. 4 is a timing diagram on the receiving side. 4CK is a clock prepared inside the receiving side device and is asynchronous with the transmitting side clock. RX is a transmission pattern sent from the transmitting side and is asynchronous with 4CK. 1a is the Q output of DF/Fl in FIG. 2, which rises at the rise of RX. 2a is a signal obtained by sampling the states of 18 signals at the Q output of DF/F2 at the rising edge of 4CK. 3a is the Q output of D-F/F3, 28
This is a signal obtained by sampling the signal state at the falling edge of 4CK.

RXC is the Q output of D-F/F4, and changes the state of the 3a signal to 4.
This is a signal sampled at the falling edge of zero.

DF/Fl is reset by the OR signal of 4a and 3a and the RXC signal.

Transfer data is sampled when the 1a signal is rLJ to separate clock pulses and data pulses.

That is, by using the 1a signal as a reset signal, DF/F5 is prepared, and the inverted signal of 1a is sampled at the rising edge of RX.

When there is a data pulse, RX rises in the inverted signal rHJ section of 1a, so the Q output of DF/F5 is rH
J, and if there is no data pulse, the inverted signal r of 1a
In the HJ section, there is no change in RX12, so D-F/F
The output RXD of No. 5 becomes "L".

FIG. 5 is a timing diagram on the transmitting side. 2CK is a clock prepared inside the transmitting side device and is asynchronous with the receiving side clock. The 6a signal is a signal obtained by dividing the Q output of DF/F6 into 2CK by A.

TXC is an inverted signal of 68 signals, and data TXD is output in synchronization with TXC. The 7a signal is a signal obtained by sampling the state of the 6a signal at the falling edge of 2CK.
The 8a signal is a signal obtained by sampling the state of the 7a signal at the falling edge of 2CK.

The transfer data TX is sent to the AND gate 14 as a signal TXD.

It is generated by inputting data pulses obtained by inputting signals 6a, 7a, and 8a and a synchronous clock pulse obtained by manually inputting signals TXC and 7a to AND gate 13 to OR gate 5.

〔Effect of the invention〕

As explained above, this invention uses a data formant in which synchronized clock pulses and data pulses are arranged alternately, so that data can be transmitted on a single wire, at high speed, and with low current consumption without using a complicated modulation/demodulation circuit. This has the effect of making it possible to construct a transfer system.

[Brief explanation of the drawing]

FIG. 1 (al is the same as the transfer pattern format of the present invention,
Figure 1 (bl is data ro, transfer pattern format diagram when L 1. sail 1), Figure 1 fcl is data r
Transfer pattern format diagram when o, O, 0, 0, OJ, Figure 1 fd+ is data rL L 1.1. I
2 is a circuit diagram of a receiving device according to the present invention, FIG. 3 is a circuit diagram of a transmitting device according to the present invention, FIG. 4 is a timing diagram of the receiving circuit, and FIG. 5 is a transmission pattern diagram for the case of J. FIG. 3 is a timing diagram of the circuit. 1-8...D F/F 9-11...Inverter 12...NAND gate 13, 14...AND gate 15...OR gate E6...Synchronization pulse 17 ...Applicant for Data Pulse and above Seiko Electronics Industries Co., Ltd. Agent Patent attorney Keisuke Hayashi ＾ U CY-SEN

Claims (2)

[Claims] (1) Alternately output synchronization pulses and data pulses,
A single-wire synchronous communication method characterized by performing data communication between asynchronous devices over a single wire by determining data based on the presence or absence of a data pulse after a synchronization pulse. (2) A communication modem characterized in that the single-wire synchronous method is combined with a plurality of DF/Fs and gates to enable data transmission and reception at a clock rate four times the communication rate.