JPS59128848A - Storage exchange type data transmission system - Google Patents

Abstract

PURPOSE:To reduce the transmission delay time by starting the output to a terminal before the receiving of a data transmitted from a transmission section is finished at a receiving side. CONSTITUTION:A transmission data A inputted from a terminal TM is inputted to a transmission buffer circuit 5. A packet combining circuit 6 combines a data of the circuit 5 into a packet and inputs the result to a packet exchange control circuit 7 together with transfer speed information outputted from a transfer speed setting circuit 16 of a receiving section. The circuit 7 transfers the packet to a device to be transmitted. On the other hand, the receiving section decomposes a received packet signal at a packet decomposing circuit 8, a data section is stored in a receiving buffer circuit 11 and the transfer speed information is inputted to a storage circuit 15. A parameter decision circuit decides a prescribed value from a signal from the circuits 15, 16, and inputs the value to a receiving output control circuit 13. On the other hand, a receiving data amount detecting circuit 12 counts the data amount of the circuit 11 and feeds a counted value to the circuit 13. The circuit 13 starts an output of the data of the circuit 11 when a prescribed value is coincident with this counted value.

Description

[Detailed description of the invention] [Technical field to which the invention pertains] The present invention relates to a store-and-forward data transmission system in which data transmission devices having an M-product exchange function are interconnected and data is transmitted between arbitrary data transmission devices. Regarding. In particular, it relates to improvements based on store-and-forward (to reduce transmission delay time).

[Description of prior art]

Data transmission in a conventional store-and-forward data transmission system will be explained using a specific example. As shown in FIG. 1, it is assumed that data transmission devices STI to ST4 are interconnected. In addition, terminals TMI to TM8 are connected to each device,
Each of these terminals outputs transmission data in the format shown in FIG. This data includes a destination address ADD indicating the destination terminal station and terminal, transmission information 1DATA, and an error detection code CHK for detecting code errors.
It consists of

The transmission section of each data transmission device STI to ST4 receives the transmission data from the terminal, and upon completion of reception, determines whether or not there is a code error, and if it is determined that this is correct, the data transmission device indicated by the address section Transfer navel data,
If it is determined to be an error, the data will not be transferred. Data transfer between each data transmission device is performed by a bucket exchange method in this example. In the packet switching method,
For example, when transferring data to the data transmission devices STI to ST3 shown in FIG. 1, the packet signal is relayed through the device ST2 or Sr1 and has a length that improves the transmission efficiency or shortens the transmission delay time. Assemble and transfer to destination. FIG. 3 is a time chart showing the state in which packet signals are assembled and transmitted. That is, the transmission data (al) in FIG. 3 is assembled into a bucket signal (b
This is transmitted to the receiving unit of the other device (as shown in C1), and the receiving unit further decomposes this bucket signal to obtain a signal in the original format (such as di).

The receiving unit of the other party's device receives the packets that are sent sequentially, and when all the packets are ready, it returns to the data format shown in FIG. 2, and outputs this to the terminal as received data.

However, in such a conventional method, since the receiving device starts outputting to the terminal when all received information is completed, the transmission delay time is long.

[Purpose of the invention]

The present invention improves this, and aims to shorten the transmission delay time between converting it into a signal suitable for storage and forwarding, transmitting it, returning it to the original predetermined signal format at the receiving side device, and transmitting it. shall be.

[Features of the invention]

In the present invention, in the transmitting unit of the data transmission device, the transfer is started before the reception of the transmitted data from the terminal is completed,
On the other hand, the receiving section is characterized in that it starts outputting to the terminal before the reception of the data divided and transmitted from the transmitting section is completed.

[Explanation based on examples]

Next, embodiments of the present invention will be described in detail with reference to the drawings. In the following 8 explanations, the present invention will be explained by connecting the data transmission devices STI to ST4 to each other to form a data exchange network as shown in FIG.
An example will be explained in which the present invention is implemented in a system that transmits data between each other.

The format of data input from the terminal to the transmission device is shown in FIG. FIG. 4 shows a time chart of the transmission procedure according to the embodiment of the present invention.

In the transmitting section of the data transmission devices STI to ST4, the terminal TM
Transmission data supplied from I to TM8 (Figure 4(a))
is converted into a packet signal and transferred to the device indicated in the address field (FIG. 4(b)). At this time, information M(S) indicating the transfer speed with the terminal is added to the first data sent. Furthermore, when receiving the transmission data input from the terminal is completed, it is determined whether there is a data error or not, and the result is notified to the transmission destination device at the same time as the transmission data ends.

On the other hand, the receiving section accumulates data transmitted as a bucket signal and simultaneously counts the amount of received data. This count value is the information sent from the transmitting station (
When a certain value (N) (Fig. 4 (C)) determined from the transfer speed between S) and the output terminal is reached, the accumulated data is sequentially sent to the terminal in the format shown in Fig. 2. It is converted into a signal and output. After that, the data that is sent sequentially is accumulated and controlled so that it is continuously output to the terminal.

The data transmitted from the receiver to the terminal (FIG. 4(d)) has a different speed from the data received by the transmitter from the terminal (FIG. 4(a)).

If a data error is indicated in the transmission data end notification received after this, or if there is no output data before receiving the transmission data end notification, the terminal adds a CHK code that allows the terminal to detect the code error. Stops output immediately.

On the other hand, if the received transmission data end notification indicates that there is no data error, an error detection code is added to all data and output is ended. As described above, in the transmission method of the present invention, data transmission delay time can be shortened by starting data transmission to a terminal before all data is received.

FIG. 5 is a block diagram of a transmission device used in the data transmission system according to the embodiment of the present invention. In FIG. 5, TM is a terminal. Input data from the terminal enters the transmitting section, passes through the receiving interface circuit 1, and is sent to the data end detection circuit 2,
It is distributed to error detection circuit 3, address detection circuit 4, and transmission buffer circuit 5. The detection outputs of the error detection circuit 3 and the address detection circuit 4 and the subsequent outputs of the transmission buffer circuit 5 are input to a packet assembly circuit 6, and the output thereof is input to a packet exchange control circuit 7. The packet switching control circuit 7 is coupled to other data transmission devices via lines.

The signal received by the packet switching control circuit is input to the packet disassembly circuit 8 of the receiving section. The output of the bucket decomposition circuit is distributed to an address storage circuit 10, a reception buffer circuit 11, a reception output control circuit 13, and a storage circuit 15.

The data amount detection circuit 12 counts the amount of data accumulated in the reception counter circuit 11, and its output is connected to the reception output control circuit. The error detection code generation circuit 9 generates an error detection code according to the output of the reception output control circuit 13 and supplies it to the reception output control circuit 13. The transfer rate setting circuit 16 sends a signal according to the setting contents to the packet assembly circuit 6 of the transmitting section.
and is applied to the parameter determining circuit 17 of the receiving section.

The parameter determination circuit 17 is connected to the storage circuit 15 and provides a parameter value output to the reception output control circuit 13.

The output signal of the reception output control circuit 13 is configured to be transmitted to the terminal TM via the transmission interface circuit 4.

Next, the operation of the device configured in this way will be explained.

Transmission data A input from the terminal TM is converted into a TTL level signal by the reception interface circuit 1 and then input to the transmission buffer circuit 5, and the address of the destination device and terminal is detected by the address detection circuit 4. be done.

The packet assembling circuit 6 packetizes the data in the transmission buffer circuit 5, and writes the address output from the address detection circuit 4 together with the transfer rate information (S) output from the transfer rate setting circuit 16 to the terminal in the header part of the packet. 2) and inputs it to the packet switching control circuit 7. Further, when the data end detection circuit 2 detects the end of the transmitted data, it notifies the packet assembly circuit 6 along with the result of the data error detected by the data error detection circuit 3. Upon receiving this notification, the packet assembling circuit 6 creates a data end notification packet (P in FIG. 4 fbl) indicating the presence or absence of data errors. The packet switching control circuit 7 transfers the packet to the destination device according to the packet switching protocol using a known method.

On the other hand, in the reception section, the received packet signal is decomposed by the bucket decomposition circuit 8, and the data part is decomposed by the bucket decomposition circuit 8.
1, the transfer rate information section is input to the storage circuit 15, and the address section is input to the address storage circuit 1o. The parameter determination circuit 17 determines a constant value (N) from the signals from the storage circuit 15 and the transfer rate setting circuit 16, and inputs it to the reception output control circuit 13.

On the other hand, the received data amount detection circuit 12 includes the reception data amount detection circuit 1
1, and inputs the counted value to the reception output control circuit 13. In the reception output control circuit 13, when the constant value (N) and this count value match, the reception section sofa circuit 11 starts outputting data following the address stored in the address storage circuit 10.

After that, the packet signals that are sequentially received are sent to the reception buffer circuit 1.
Accumulate to 1. Furthermore, when the bucket decomposition circuit 8 receives a transmission data end notification indicating that there is a data error,
The reception output control circuit 13 is notified, the error detection code created by the error detection code generation circuit 9 and corresponding to the data that has already been output is inverted and outputted, and data output is immediately stopped. On the other hand, when receiving a transmission data end notification indicating that there is no data error, an error detection code is added to all data in the reception buffer circuit 11, and then the output ends. The output signal is output to the terminal via the transmitting interface circuit 14.

〔Effect of the invention〕

As described above, in the present invention, the transmitting section starts the transfer before the reception of the transmission data from the terminal is completed, and the receiving section starts the transfer before the reception of all the data transmitted from the transmitting section of another device is completed. Since data output to the terminal has started, the transmission delay time can be reduced.

Furthermore, since the transfer rate between the transmitting station and the terminal is notified, the transmission delay time can be reduced even in data transmission between terminals with different speeds.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram showing the system configuration of an exchange type data transmission method. FIG. 2 is a diagram showing the format of data transmitted between terminals in an exchange type data transmission system. 3 (al to (dl) are time charts for explaining data transmission in the conventional method. FIG. 4 (a) to (dl are time charts for explaining one embodiment of the present invention. Block configuration diagram of a transmission device used in the invention. STI to ST4... data transmission device, TMI to TM8
... terminal device, 1 ... reception interface circuit,
2... Data end detection circuit, 3... Data error detection circuit, 4... Address detection circuit, 5... Transmission buffer circuit, 6... Packet assembly circuit, 7... Packet exchange control circuit , 8...Packet decomposition circuit, 9...Entertainment detection code creation circuit, 10...Address storage circuit,
DESCRIPTION OF SYMBOLS 11... Reception buffer circuit, 12... Data amount detection circuit, 13... Control circuit, 14... Transmission interface circuit, I5... Storage circuit, 16... Transfer rate setting circuit, 17. ...Parameter determination circuit. Patent Applicant NEC Corporation -7 Agent Patent Attorney Naotaka Ide □・2nd Mutual 3 M4 Drawing Procedure Amendment (Method) May 2, 1930 Japan Patent Office Moss Kazuo Wakasugi 1 , Indication of the case Patent Application No. 4032 of 1988 2, Title of the invention % Q's 'Example 1 stage (z, to the clairvoyant' 3, Relationship with the person making the amendment) Address of the patent applicant Tokyo 5-33-1-4 Shiba, Minato-ku, Agent 6, Number of inventions increased by amendment None 7, Specification subject to amendment, page 11, line 17 to page 12, line 1, “3
Figure: Time chart. Correct J as follows. "Figure 3 is a time chart for explaining data transmission in the conventional method. Figure 4 is a time chart for explaining one embodiment of the present invention."

Claims (1)

[Scope of claims] In a data transmission system configured to perform data communication using continuous signals in a predetermined format between the data transmission device and the terminal, and to perform store-and-forward data transmission between the data transmission devices, The transmitting unit of the data transmitting device includes means for adding information indicating the data transfer rate with the terminal, and the receiving unit of the data transmitting device includes a means for adding information indicating the data transfer rate with the terminal, and the receiving unit of the data transmitting device is configured to include a means for adding information indicating a data transfer rate with the terminal, and a receiving unit of the data transmitting device includes a means for adding information indicating a data transfer rate with the terminal. A store-and-forward data transmission system characterized by being controlled to start outputting data to a terminal when the terminal reaches the destination.