JPS5883881U

JPS5883881U - Vertical synchronization signal generation circuit

Info

Publication number: JPS5883881U
Application number: JP18067881U
Authority: JP
Inventors: 相良　喜久雄; 小島　正典
Original assignee: 三菱電機株式会社
Priority date: 1981-12-03
Filing date: 1981-12-03
Publication date: 1983-06-07

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図はこの考案の背景となりかっこの考案に−　　。適用されるＶＴＲの特殊再生モードにおける擬似垂直同
期信号の切換回路の回路図である。第２図は従来の擬似
垂直同期信号発生回路２０の回路図である。第３図は従
来のＶＴＲにおける通常再生モードの出力波形図である
。第４図は擬似垂直同期信号発生回路２０の各部の出力
波形図を示す。第５図はこの考案の一実施例の垂直同期信号発生回路５
０の回路図である。第６図はこの実施例の垂直同期信号
発生回路５０の各部の出力波形図である。図において、５２．５４は遅延回路、５３はＥＸＮＯＲ
ゲートを示す。 −＼・ソｒ゛ｔ７７月鹸イ富ｈ　　　　　−一−−−−
−−「−−一一一−−−−−−−−−−１−一−−一一
一一一一−−−ゴヒ直［０賽月信＋４４　　　　　　−
一一一一一一一丁１，１−一−−−−−−−−−−−−
−１−丁一一一一一一一一一７、デＨ」−ｍ− Ｍ−一Figure 1 is the background to this idea and the idea of parentheses. FIG. 3 is a circuit diagram of a pseudo vertical synchronization signal switching circuit in a special reproduction mode of a VTR to which the present invention is applied. FIG. 2 is a circuit diagram of a conventional pseudo vertical synchronization signal generation circuit 20. As shown in FIG. FIG. 3 is an output waveform diagram of a conventional VTR in normal reproduction mode. FIG. 4 shows an output waveform diagram of each part of the pseudo vertical synchronization signal generation circuit 20. FIG. 5 shows a vertical synchronizing signal generating circuit 5 of an embodiment of this invention.
0 is a circuit diagram. FIG. 6 is an output waveform diagram of each part of the vertical synchronizing signal generating circuit 50 of this embodiment. In the figure, 52 and 54 are delay circuits, and 53 is an EXNOR
Showing the gate. -＼・Sort 77 month Kenifu h -1------
--"--111---------1-1--111111---Gohi Nao [0 Saigetsushin +44 -
111111 1, 1-1---------------
-1-Ding 11111117, DeH''-m-M-1

Claims

[Scope of utility model registration request]

(1) In a special playback mode different from the normal playback mode of a magnetic recording/playback device, a pseudo vertical synchronization signal is generated to adjust the vertical synchronization of the reproduced image when switching heads, and the head switching signal is a first delay means for delaying the output signal of the first delay means by a second delay time; and a second delay means for delaying the output signal of the first delay means by a second delay time; A vertical synchronizing signal generation circuit comprising pulse generation means for generating a pulse having a time width corresponding to the second delay time in response to the output signal of the second delay means.

(2) The pulse generating means includes a circuit for determining a coincidence state between the output signal of the first delay means and the output signal of the second delay means, as described in claim (1) of the utility model registration. Vertical synchronization signal generation circuit.