JPS616912U

JPS616912U - Azimuth error correction circuit for playback equipment

Info

Publication number: JPS616912U
Application number: JP9209084U
Authority: JP
Inventors: 隆生川崎
Original assignee: 日本ビクター株式会社
Priority date: 1984-06-20
Filing date: 1984-06-20
Publication date: 1986-01-16

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図は本考案になる再生装置のアジマス誤差補正回路
の一実施例を示す図、第２図は従来の再生装置のアジマ
ス誤差補正回路を示す図、第３図は遅延回路の具体的な
回路例を示す図、第４図は第３図の遅延回路の具体的な
回路例を用いて構成した本考案になる再生装置のアジマ
ス誤差補正回路の一実施例を示す図である。ｌａ，ｌｂ・・・増幅回路、２・・・加算回路、３・・
・加算回路２の出力端子、４・・・位相弁別回路、６ａ
，６ｂ・・・遅延回路、Ｉ−｛ａ，．Ｈｂ・・・磁気
ヘッド。FIG. 1 is a diagram showing an embodiment of the azimuth error correction circuit of the playback device according to the present invention, FIG. 2 is a diagram showing the azimuth error correction circuit of a conventional playback device, and FIG. 3 is a diagram showing a specific example of the delay circuit. FIG. 4 is a diagram showing an example of an azimuth error correction circuit of a reproducing apparatus according to the present invention, which is constructed using a specific circuit example of the delay circuit shown in FIG. 3. la, lb...amplifier circuit, 2...addition circuit, 3...
- Output terminal of adder circuit 2, 4...phase discrimination circuit, 6a
, 6b...delay circuit, I-{a, . Hb...magnetic head.

Claims

[Scope of utility model registration request]

first and second heads each having a gap corresponding to each track obtained by dividing one signal track width into upper and lower parts; and first and second heads that delay respective reproduction signals reproduced by the first and second heads. The phase difference between the outputs of the second delay circuit and the first and second delay circuits is detected, and this phase difference is fed back into one of the first and second delay circuits. 1. An azimuth error correction circuit for a reproducing apparatus, comprising: a phase discrimination circuit that changes the delay time; and an addition circuit that combines the outputs of the first and second delay circuits.