JPS5835294B2 - Multiprocessor processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Regarding the multiprocessor processing method of the present invention, in particular, when a plurality of processors such as microcomputers are used to realize one processing device, information transmission between each processor increases the program load. This paper relates to a multiprocessor processing method that allows processing to be performed without any problems.

When realizing a processing device using a processor such as a microcomputer, it is not possible to obtain the required capacity with just one processor, and it is often done to distribute the processing by connecting two or more processors in multiple ways. ing.

When these processors share processing and operate independently, mutual processing requests inevitably occur between these processors.

The present invention relates to a method for transmitting processing requests between processors.

Here, in order to simplify the explanation, two processors will be assumed.

FIG. 1 shows an example of a processing request transmission circuit between processors in a processing device using two processors.

PA and PB are processors such as microcomputers, MEM-A and MEM-B are memories for storing programs, IR and DRI-n are program control registers, and INTC is an interrupt control circuit.

BUS-A and BUS-B are system buses for connecting PA or PB with memory and register circuits, and are composed of an address bus, a data bus, and other control signals.

A□-A n is a register address in BUS-A, and B 6 "B n is a register address in BUS-B.

PA and PB read programs from memory via their respective system buses and independently process them based on the instructions.

The conventional system will be explained with reference to FIG. 1, assuming that the PA issues an inter-processor processing request to the PB.

When a processing request for PH occurs in PA, the processing request factor is written to register IR, and P
At Bf, PA writes data necessary for the processing to one or more of registers DR1 to n.

Further, the interrupt control circuit 1NTc generates an interrupt IB to PB due to the processing factor written by PA to the register IR.

On the other hand, the PB reads the IR upon detecting the iB, and after determining the processing request, reads either DRl or n as necessary and executes the processing.

If you use PBF and clear IR after this process, P
When the next processing request to PB occurs, A confirms that the IR has been cleared and then returns the IR and DR1 to n.
can be written to.

The above processing is the same when a processing request is issued from PB to PA, and requires an equivalent circuit, although not shown in FIG.

However, the drawbacks of the method described above are iR and DR1~
It requires as many registers as n, and since it is program controlled, it is necessary to allocate an address to each register.

This results in an increase in hardware on the PA and PB sides, and, for example, when a processing request is made from the PA to the PB, the PA
The side program has many addresses (A.

~An) needs to be accessed depending on the processing request contents, and, like the PB side program, the load on the program is also large.

Also, as mentioned earlier, when the PA issues the next processing request to the PB, it is necessary to confirm that the IR has been cleared, and if the IR has not been cleared, the PA will wait until it is cleared. Waiting results in a decrease in processing capacity.

An object of the present invention is to eliminate the drawbacks of the above-mentioned conventional methods, and for this purpose, the present invention provides a processing device comprising a plurality of independently operating processors, in which a predefined fixed-length data format is established between the processors. First-in, first-out, accumulating data with
A register group is provided, processing requests between the processors are accumulated in the first-in first-out register group, and processing requests are transmitted from one processor to the other processor.

Hereinafter, the present invention will be explained with reference to the drawings.

FIG. 2 is a block diagram of a multiprocessor system according to an embodiment of the present invention. In the figure, the same names as those in FIG. Writes from PA and reads from PB, FIFo-2 is the same (this first-in
It is a first-out register group and is written from PB to P.
It is read from A.

Also, AO is the register address in BUS-A, B
o is a register address in BUS-B.

Similar to the explanation in the case of Fig. 1, to explain the case where a processing request is made from PA to PB, when a processing request occurs, the PA program sends a byte i indicating the cause of the processing request.
and the accompanying data D1 to Dn are successively written to the same address (Ao).

FIFo-1 is composed of a group of registers as shown in FIG. 3, and immediately shifts the contents written from PA via BUB-A to BUS-B.

Therefore, from PA byte i and accompanying data D1~
When Dn are written in succession, they are stored in the register R8-R,n closest to BUS-B.

Also, at this time, when information is stored in register R8, BUS-
It becomes possible to read the contents of register R8 via B,
The circuit is configured so that INTC detects this state, and 1NTC generates an interrupt IB to PB.

When PB detects interrupt IB, it reads the same address (BO) n + 1 times in succession (thereby, byte i
and data D1 to Dn can be read.

This means that the FiFo register R6 is PB in Figure 2.
This is because the contents of registers R8 to Rn are immediately shifted to the BUS-B side when read from f.

As described above, if the next processing request is not generated in the PAF, the stored information disappears and the interrupt IB is canceled after the PB reads FIFo-1 n + 1 times.

In addition, if the next processing request occurs in PA before PB finishes reading the above n bytes, PA immediately stores it in FIFo-1 in the same way as described above, and sends it to BUS in card order.
- Shifted to the B side.

In this way, P processing requests can be stored in FIFol, and the FA is not forced to wait as in the system of FIG.

Figures 2 and 3 (here, the transfer from PA to PB in one processing request is fixed length (n + 1 in Figure 3)
Byte), regardless of the processing request contents, P
B is FIF per processing request.

-1, it is sufficient to always read the same number of times, and the program processing is further simplified.

The above has described the case where a processing request is made from PA to PB, but the reverse case is also applicable except when FIFo-2 is used.

Compared to the conventional method described in FIG. 1, the processing method according to the present invention requires an extremely small number of program control register addresses, and because FiFo can use a commercially available LSI, the amount of hardware is small and the program load is low. Reduce.

Furthermore, there is no waiting time at PA or PB for transfer of processing requests, and by making the transfer unit a fixed length, it is possible to improve processing performance.

[Brief explanation of drawings]

Figure 1 shows a conventional example of an inter-processor processing request transmission circuit;
The figure is a block diagram of a multiprocessor system according to an embodiment of the present invention, and FIG. 3 is an example of the configuration of the first-in first-out register group shown in FIG. In Figure 2, PA and PB are processors, BUS-A
and BUS-B are system buses, MEM-A and MEM-B
is a memory, FiFo-1 and FiFo-2 are first-in/fast-out register groups, and 1NTC is an interrupt control circuit.

Claims (1)

[Claims] 1. In a processing device composed of a plurality of independently operating processors, instructions in a predefined fixed length data format are stored between the processors,
A first-in/first-out register group is provided to sequentially shift the fixed length instructions in instruction units, and processing requests between the processors are accumulated in the first-in/first-out register group, and one processor transfers processing requests from one processor to the other. A multiprocessor processing method characterized by transmitting processing requests to computers using interrupts.