JPS6367702B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a system for locking signals on a bus in an information processing apparatus that couples a plurality of data processing units.

[Description of prior art]

Conventionally, in this type of lock operation method, when information is transferred accompanied by a lock signal from the bus, a flag is provided in the unit receiving the lock operation to store it, and the information is transferred in response to the first access from the bus accompanied by the lock signal. It sets the lock flag, receives a series of subsequent operation information, and sends a signal to reset the lock flag with the last access, thereby terminating the lock operation. Furthermore, when a unit whose lock flag is set is accessed with another lock signal, the unit is configured to return a lock busy response.

As you can see from the above, in the past, you could not tell whether a site was locked or not until you actually accessed it. Therefore, a unit that attempts to perform a lock operation and waits for a lock busy response ends up repeating access accompanied by a lock signal, and has to wait for the lock flag to be released.

FIG. 1 shows a plurality of data processing units 100, 1.
01, input/output control units 110, 111,
This is a conventional basic information processing device in which a main memory 120 is coupled to a common bus 10, and this will be described in more detail.

First, we will discuss the operation in which data processing unit 100 reads one word from main memory 120 during information transfer, changes its contents, and stores it at the same location (address) from which it was previously read. During this operation, when the data processing unit 101 attempts to perform the same operation as described above, the data processing unit 101 reads out the data read by the data processing unit 100, and the data processing unit 10
Since the data processing unit 101 writes further data on top of the data previously written by the data processing unit 0, there arises the problem that the data written by the data processing unit 100 is lost.

Conventional locking arrangements were devised to avoid this. This is to prevent similar processing by the data processing unit 101 while the data processing unit 100 performs the above-mentioned operation. Conventionally, such a mechanism has been used to prevent the operated unit (the In the example, there is a flag that exists in the main memory) that remembers that the above operation is being performed, and a flag that, when the flag is ``1'', responds ``reject'' to a request for the above operation from another unit. It was realized with a circuit that generates

[Purpose of the invention]

The present invention solves the above problems by displaying a lock signal on the bus.
It is an object of the present invention to provide a data processing device that can reliably perform a lock operation without unnecessarily repeating bus cycles.

[Key points of the invention]

The present invention combines multiple information processing units,
In a data processing device equipped with a common bus for transferring information between any two of the units, each of the information processing units has a series of operations divided into several bus cycles for each other. The present invention is characterized by comprising means for displaying what is being done on the common bus, and means for holding this display until the end of the operation.

[Explanation based on examples]

Next, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a block diagram of a data processing unit according to an embodiment of the present invention. In FIG. 2, reference numeral 10 is the common bus 40 and 5.
0 are bus 10 and data processing unit 10 respectively.
These are a driver and a receiver element that connect 0 to 0.
20 displays "lock operation in progress" and the control circuit 20
0, and 30 is a bistable circuit that temporarily stores whether or not there is a lock indication on the bus. The control circuit 200 is a bistable circuit 30
It is connected to the input and output sides of the The data processing unit 100 that wishes to carry out the above-mentioned continuous operation will transmit the signal 11 on the bus 10 if it is allocated the right to use the bus.
is received via the receiver element 50, and the clock signal 202 is supplied to the bistable circuit 30 and taken in.
The output 31 of the bistable circuit 30 is determined by the control circuit 200. When signal 11 is not present on the bus, control circuit 200 uses set signal 203 to close bistable circuit 2.
0 and uses driver 40 to connect common bus 1.
Output as 0 above signal 11. In addition, the control circuit 2
00, and when the signal 11 is present, the set signal 203 is not output and execution of the scheduled continuous operation is canceled.

Next, an example of the timing of this operation will be explained using FIG. 3. DVLD in the figure represents the timing of information transfer on the bus, and LOCK represents the timing of information transfer on the bus 10.
represents signal 11 above. The bus cycles indicated by 1 to n in the figure represent continuous operation, and are indicated by broken lines.
A ₁ and A ₂ represent bus cycles by other units. Here, the unit that is about to perform continuous operation determines the presence or absence of the LOCK signal at timing _T1 , and sets the lock signal at timing _T2 during one bus cycle. Thereafter, continuous operations 1 to n are performed, and the lock signal is reset with the output of the last bus cycle n. By performing the above-described operations, competition with similar continuous operations by other units during continuous operations can be avoided.

〔Effect of the invention〕

The present invention provides a lock indication from each processing unit on a common bus, thereby solving the inconvenience caused by competition between successive operations, while allowing each processing unit to perform memory read/write operations that do not involve locking operations without being hindered. In addition, it is possible to operate units connected to other buses, and it is possible to obtain the effect that the bus is not unnecessarily occupied.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a basic information processing device including a plurality of data processing units. FIG. 2 is a block diagram of a data processing unit according to an embodiment of the present invention. FIG. 3 is a timing diagram of a bus cycle according to an embodiment of the present invention. 10... Common bus, 20, 30... Bistable circuit, 40... Bus driver, 50... Bus receiver element, 100, 101... Data processing unit, 110, 111... Input/output control unit, 1
20...main memory, 200...control circuit.

Claims (1)

[Scope of Claims] 1. In a data processing device that connects a plurality of information processing units and is equipped with a common bus that transfers information between any two of the units, each of the information processing units has The device is characterized by comprising means for displaying on the common bus that a series of operations divided into several bus cycles are being performed for the unit, and means for holding this display until the end of the operation. data processing equipment.