JPS58181160A - Controlling system of emergency operation - Google Patents

Abstract

PURPOSE:To obtain information useful for the search of a cause by which an emergency controlling circuit is started, by saving the internal state of a CPU into a main storage device when the start of the emergency controlling circuit is requested and starting the emergency control operation after it is saved completely. CONSTITUTION:If a normal program is stopped by some fault or an error of the program, a controlling circuit 6 and a supervisory timer 7 are started through an OR circuit 5 by an overflow signal 31 of a fault detecting timer 3 or an abnormality signal 4 from a system supervisory device. The internal state of a CPU1 is saved in a prescribed area of a main storage device 2 by a control signal 61 from the circuit 6. After it is saved completely, a completion signal 62 is outputted to start an emergency controlling circuit 9 through an OR circuit 8. Then, initialization of the CPU1 and controls of reloading of the program and etc. are performed to reconstitute a data processing device. The timer 7 is reset by the signal 62 to indicate the completion of the saving operation.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for controlling the operation of an emergency control circuit that is activated when a normal state occurs and reconfigures a normal system. As an emergency operation control method, a central control unit or a system monitoring device monitors the execution status of the program, and if normal program execution is stopped for some reason, the emergency control circuit is activated from these devices. Sends a start signal to.

In the emergency control circuit, a method is known in which the initial setting program of the central control unit is reloaded and the data processing apparatus is reconfigured.

According to this method, the central control unit is initialized when reconfiguring the data processing equipment, so the internal state of the central control unit is not saved, which makes it difficult to find the cause of the activation of the emergency control circuit. However, there is no other way than to estimate it from the contents stored in the main storage device, and there is a drawback that it is difficult to perform accurate cause analysis.

In accordance with the activation request signal of the emergency control circuit, the present invention first saves the internal state of the central control unit in the main memory,
Operation of the emergency control circuit that solves the above-mentioned drawbacks by configuring the emergency control operation to be activated after waiting for the completion of the save operation, and that can obtain information useful in searching for the cause of activation of the emergency control circuit. The objective is to provide a control method.

The present invention includes a first means activated by an activation request signal of an emergency control circuit to save the internal state of the central control unit in a predetermined area of a main memory; This emergency operation control method is characterized in that it has a third means for starting the operation of the emergency control circuit by monitoring the time until the operation of the first means is completed.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram illustrating details of the present invention.

The central control device 1 and the main storage device 2 are connected, and the overflow signal 31 of the fault detection timer 3 that monitors the execution of the program of the central control device 1 (3) indicates a system abnormality from the system monitoring device (not shown). A signal 4 is input to an OR circuit 5. The output of the OR circuit 5 is input to the control circuit 6 and the monitoring timer 7, and the control signal 61 from the control circuit 6 is connected to the central controller 1 in order to save the internal state of the central controller 1 to the main memory 2. .

Further, the completion signal 62 of the control circuit 6 and the overflow signal 71 of the monitoring timer 7 are input to the OR circuit 8, and the output of the OR circuit 8 is input to the emergency control circuit 9. Furthermore, the fault detection timer 7 bit signal 11 from the fault detection timer 3 is arranged to reset the fault detection timer 3.

Next, the operation of the embodiment of the present invention will be explained.

When the central control device 1 is in a normal program execution state, it outputs the reset signal 11 before the failure detection timer 3 overflows, suppresses the generation of the overflow signal 31, and also prevents the system abnormality signal from the system monitoring device. The occurrence of (4) is also suppressed. When normal program execution is stopped due to a failure or an error in the program, either the overflow signal 31 of the failure detection timer 3 or the abnormality signal 4 from the system monitoring device is generated, and the The control circuit 6 is activated through the circuit 5, and the monitoring timer 7 is activated. Control signal 6 from control circuit 6
1, a general-purpose register in the central controller 1;
The internal state of the flip-flop etc. is saved in a predetermined area of the main storage device 2. The reason why the area to be saved is determined in advance is that unless it is an area that will not be destroyed even after the system is reconfigured, it cannot be used to analyze the cause of the failure.

Thereafter, when the internal state of the central control device 1 has been saved to the main storage device 2, a completion signal 62 is output, and the initial setting and program of the central control device 1 are started by activating the emergency control circuit 9 through the OR circuit 8. The data processing device is reconfigured by controlling reloading and the like. Furthermore, the completion signal 62(5) instructs the completion of the save operation by resetting the monitoring timer 7. This is because the overflow time of the monitoring timer 7 is set to be slightly longer than the time required for the control circuit 6 to save the internal state of the central control unit 1 to the main storage device 2.

As a result, when a failure occurs that prevents a save operation from occurring, the overflow signal 71 of the monitoring timer 7 is output, and the emergency control circuit 9 can be activated through the OR circuit 8, thereby preventing a normal save operation. Upon completion of the process, the monitoring timer 7 is reset to prevent the overflow signal 71 from being generated.

FIG. 2 is a block diagram illustrating the configuration of the control circuit 6 in more detail. a counter 63 connected to the output of the OR circuit 5 and incremented at a constant cycle; a read-only memory 64 that stores control information to the central controller 1 addressed by the counter 63; includes a register 65 that latches read information and outputs a control signal 61 and a completion signal 62.

(6) FIG. 3 is a diagram showing details of the information latched in the register 65, including a field SR indicating the number of the register to be saved in the main storage device 2, and a field DA indicating the save destination address.

It includes a field PR that instructs the start of a save operation and a field ED that instructs the completion of this operation.

Next, the operation of the control circuit 6 will be explained with reference to FIGS. 2 and 3. When the output control circuit 6 of the OR circuit 5 is activated, the counter 63 advances by +1 from the initial value, the read-only memory 64 is accessed, and the control information is read into the register 65.

Referring to FIG. 3, the register 65 contains the number of the register to be saved in the main memory 2, the address of the save destination, and the start instruction for the save operation, so these information is sent to the control signal to the central controller 1. 61, the central control unit 1 can execute a save operation to the main storage device 2. The above-described save operation is performed by incrementing the counter 63 at regular intervals, and reading from the read-only memory 64 accessed by the value (7) of the counter 63 when all necessary internal state save operations are completed. Completion indication field ED of register 65 that latches information
The operation of the control circuit 6 is completed by configuring the control circuit 6 to be "1"".

Although one embodiment of the present invention has been described above by showing a specific configuration, the present invention is not limited to this embodiment. For example, the block that controls the saving operation of the internal state of the central control device 1 shown as the control circuit 6 to the main storage device 2 does not need to be an independent block from the central control device 1; It goes without saying that there is no problem even if the device has a function to control the save operation added to a part of the microprogram.

As explained above, the present invention does not immediately start the emergency control operation by the activation signal of the emergency control circuit.
First, the internal state of the central control unit is saved in the main memory, and the emergency control operation is activated after waiting for the completion of the save operation to search for the cause of activation of the emergency control circuit ( 8) Effective information can be secured in the main memory, and the cause of failure can be analyzed more accurately than conventional methods.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a data processing device having an emergency control circuit, which is an embodiment of the present invention. 2 is a block diagram of the control circuit 6 of FIG. 1, and FIG. 3 is a block diagram of the register 65 of FIG. 2. In the figure, 1... Central control unit, 2... Main storage device, 3
...Failure detection timer, 4...System abnormal signal, 5
... OR circuit, 6 ... Control circuit, 7 ... Monitoring timer, 8 ... OR circuit, 9 ... Emergency control circuit, 31.
... Reset signal, 31 ... Overflow signal, 61
···Control signal. 62... Completion signal, 63... Counter, 64...
Read-only memory, 65...Register, 71...Overflow signal. (9) Figure 1

Claims (1)

[Claims] 1. A central controller, a main storage device, and an emergency control that is activated by a activation request signal when the central controller detects an abnormality or by an external activation request signal to reconfigure a normal system. a first means that is activated by the activation request signal and saves an internal state of the central control unit in a predetermined area of the main storage device; a second means that is activated by the user and monitors the time until the operation of the first means is completed; and a completion signal from the first means and a monitoring time overflow signal from the second means. An emergency operation control system comprising a third means for starting the operation of the emergency control circuit.