JPS61101845A - Test system of information processor - Google Patents

Abstract

PURPOSE:To prevent a phenomenon that a wrong data is erroneously judged as a correct data even when a fault is not detected even by the software by executing a program testing the normality of the entire processor at each prescribed time. CONSTITUTION:An operating system OS13, a test program control task 12 and a test program execution task 11 are stored in a main storage device 10 of an information processor and processors CPCU 14, 15 execute each instruction in the device 10. An execution task 11 in the device 10 executes a test program in the CPU 14, 15 and when a fault in the CPU 14, 15 is detected, an error message is outputted to a message output device to output a stop request to the OS 13. After the execution task 11 is executed by the CPU 14 only at the control task 12, the execution task 11 and the CPU 14, 15 are controlled so as to be executed by the CPU 13 only. Further, the control task 12 is executed at each prescribed time by the OS 13 to receive a stop request of the execution task 11 to save the next rising information to a magnetic disc.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a testing method for an information processing device, and particularly to a health check method for testing under operating system control.

[Conventional technology]

Conventionally, as failures in information processing devices, in addition to failures detected by check circuits within the devices, there are also failures that cannot be detected by the check circuits, and these failures result in failures that occur later in the operating system (hereinafter referred to as O8). This was detected in the form of a logical contradiction in software such as

[Problem that the invention seeks to solve]

However, failures detected in the form of logical contradictions in software may not be detected by software because the software is not created for the purpose of detecting hardware failures. In this case, the data would be garbled, and since the failure was detected a long time after the failure occurred, there was a fatal problem in that data recovery would be difficult.

SUMMARY OF THE INVENTION An object of the present invention is to provide a test method for an information processing device that prevents data from being garbled in the event of a failure that is not detected even in software.

[Means for solving problems]

A test method for an information processing device according to the present invention includes a test program execution task for testing a processing device connected to a main storage device, a test program control task for controlling the test program execution task, and a test program control task for controlling the test program execution task. An operating system for controlling a control task is stored in the main storage device, the operating system executes the test program control task at regular intervals, and the test program control task is the test program execution task. 7
When the test program execution task detects a failure in the processing device, it issues a request to the operating system to stop execution, and the operating system responds to this request. yr) The operating system is characterized in that execution of the operating system itself is stopped immediately after executing an emergency stop process to save information necessary for the next startup.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the test force type of the information processing apparatus of the present invention. The main storage device (hereinafter referred to as MMU) 10 contains 0813. Test program control task 12. A test program execution task 11 is stored, and processing units (hereinafter referred to as CPUs) 14 and 15 execute each instruction in the MMUIO.

The test program execution task 11 is executed by the CPU 14.

15 is executed, and when a failure of one of the CPUs 14 and 15 is detected, an error message is output to an output device (not shown), and a stop request is output to 0813. The test program control task 12 uses the CPU
The test program execution task 11 and the CPU 14.15 are controlled so that the test program execution task 11 and the CPU 14.15 are executed only by the CPU 15 after being executed by the CPU 14. 0813 executes the test program control task 12 at regular intervals, and when a stop request is input from the test program execution task 11, it performs system stop processing and collects information such as the number of the failed CPU, which is necessary when restarting the system. information is saved to a magnetic disk (not shown).

Next, the operation of this embodiment will be explained with reference to the drawings.

Figure 2 shows the test program 08 which executes the system control task 12.
3 is a schematic flowchart of the operation of the test program control task 12, and FIG. 4 is a schematic flowchart of the decimal addition instruction in the test program execution task 11.

First, when the system startup is completed, process 21 in Figure 2 is performed.
Control is transferred to test program 2, and test program control task 12 is activated. Execution of test program control task 12 is accomplished according to FIG. To test the CPU 14, process 3
1 notifies the KCPU 14 that the test program execution task 11 is executed only by the CPU 14. Next, in process 32, the test program execution task end T7 lag is set to O.
and starts the test program execution task 11.

A part of the test program execution task 11 is shown in FIG.

When the control is transferred to process 41, the CPU number to be tested and the command to be tested are sent to the message sending machine. Processing 42
Now, execute the decimal addition instruction to be tested. In process 43, the execution result of the decimal addition instruction is compared with the expected value. If the results match according to judgment @44, the process moves to step 50 and the next test is executed. If the results match in the last test, the test program execution task end flag is set to IK, and the processing of the test program execution task 11 is ended.

Thereafter, control of the test program control task 12 moves from decision 33 to process 34 in FIG. In processes 34 to 36, the CPU 15 is tested in the same manner as in processes 31 to 33.

Upon completion of the test program creation task 12, the process moves to process 22 in FIG. 2, where a one hour timer is set. After one hour has passed, the process returns from judgment 23 to process 21,
If the trial sale is executed again, the result will be K.

If the result of judgment @44 in FIG. 4 does not match, control of the program 2 moves to process 45, and the execution result in process 42 and the expected value used in process 43 are transferred to the message sending canister. do. Thereafter, in step 46, the error message is edited and output to the message output device. When control of the program is transferred to process 47, a stop request is output to 0813, and when control is then transferred to process 48, information necessary to restart the system as an emergency stop process, such as CP
Information indicating that U has failed and the failed CPU number are written to a magnetic disk (not shown).

Thereafter, when the control is transferred to 49, 0813 immediately performs a system stop process (not shown). This prevents data from becoming garbled.

In this embodiment, there were two processing devices 14 and 15 to be sampled, but it is easy to see that the present invention is applicable to information processing equipment having any number of processing devices, as long as it is one or more. I can make an analogy.

〔Effect of the invention〕

As explained above, the present invention has the ability to prevent data from becoming garbled due to malfunctions of any processing equipment by running a program that tests the normality of all processing equipment at regular intervals. effective.

[Brief explanation of drawings]

FIG. 1 is a system configuration diagram of an information processing device to which the information processing device testing method of the present invention is applied, FIG. 2 is a flowchart of the operation of the operating system 13 shown in FIG. 1, and FIG.
FIG. 4 is a schematic flowchart of the operation of the test program control task 12 shown in FIG. ). 10...Main storage device 11...Test program execution task 12...Test program control task 13...Operating system 14*15...Processing equipment. Figure 1 Figure 2 ++ Figure 3 Figure 4

Claims (1)

[Claims] A test program execution task for testing a processing device connected to the main storage, a test program control task that controls the test program execution task, and an operating system that controls the test program control task are stored in the main storage. the operating system executes the test program control task at regular intervals, and the test program control task controls the test program execution task to cause the processing devices to sequentially execute the test one by one. When the test program execution task detects a failure in the processing device, it issues a request to the operating system to stop execution, and the operating system immediately restarts the operating system after executing an emergency stop process to save information necessary for the next startup. A testing method for information processing equipment characterized by stopping the execution of the system itself.