JP3214079B2 - CPU abnormality detection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an abnormality detecting apparatus for monitoring an abnormality of a CPU suitable for application to a servo system of a VTR and detecting an abnormality of the CPU.

[0002]

2. Description of the Related Art In a servo system used for a VTR, a CPU is used for servo control, and peripheral circuits such as a capstan servo circuit are controlled based on a command from the CPU. As a method of monitoring the operation of the CPU, there is a watched dog timer (hereinafter, referred to as WDT). This WDT is a timer that performs the following operation. 1. The CPU periodically accesses the WDT and resets the WDT. 2. If it has not been accessed for a certain period of time, change the output level. This change in the output level indicates that the CPU is not operating normally. In other words, if the CPU should be accessed during a certain period of time if the CPU is normal, it is determined that there is an abnormality if there is no access after a certain period of time. As a method of using the WDT, the time of the interval at which the WDT is periodically accessed is known in advance, and a time obtained by adding a margin to the maximum time is set in the WDT, and then the operation of the CPU is started.

FIG. 5 is a block diagram showing a conventional example of a CPU control circuit including a peripheral processing circuit such as a capstan servo circuit employing the WDT. In FIG.
Numeral 1 denotes a CPU which controls various controls in the servo system. Various signals (address signals and control signals) from the CPU 1 are supplied to an address decoder 51, in which an address signal is decoded, and the decoded address data A control signal is supplied as a specific access signal to a peripheral processing circuit (such as a drive circuit for capstan servo) 52 based on the control signal.

Reference numeral 53 denotes the WDT.
3 is supplied with a decoded output from the address decoder 51, and is reset at regular intervals (periodically) because the WDT 53 is accessed by the decoded output during a normal operation of the CPU 1, so that the WDT 53 does not always overflow. It has become.

When the CPU 1 is in an abnormal state, the WDT 5
Since the WDT 53 is not normally accessed, the WDT 53 is not reset, and the CPU 1 is forcibly subjected to the highest interrupt (NMI) or reset based on a control signal obtained by overflow.

[0006] However, the CP by the WDT 53
The abnormality monitoring of U1 has the following limitations. 1. The WDT detects an abnormality that the regular processing is not performed regularly, and thus cannot be used for monitoring the irregular processing. For example, when the tape speed measurement processing is performed four times per rotation of the motor by the servo system of the VTR, there is no processing when the motor is stopped.
Attempting to use DT requires an infinite amount of time to control the motor, and WDT cannot be used. In such a VTR servo system, the CP
If the operation of U becomes abnormal and the abnormality cannot be detected, tape damage may be caused.

[0007] 2. Since the set value of the abnormal time of the WDT must be a value obtained by adding a margin to the longest time accessed in a normal operation, the detection is delayed by the margin.

[0008]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a CPU monitoring device for monitoring the operation of a CPU which has been solved without using a WDT, in order to avoid the above-mentioned problems caused by using a WDT.

[0009]

The present invention provides a CPU, a storage device storing a predetermined program to be executed by the CPU, an interrupt signal generator for requesting the CPU to start a predetermined process, A process-in-progress signal output device for discriminating when the process is being executed and when it is not, and outputting a process-in-progress signal;
An abnormality detector for detecting an abnormality of the CPU by looking at the execution signal immediately before the PU starts the predetermined processing, and when an interrupt signal is sent to the CPU, whether the previous interrupt processing has been completed. It is characterized by checking whether the CPU is abnormal or not, if not completed.

[0010]

FIG. 1 is a block diagram showing a first embodiment of a CPU abnormality detecting apparatus according to the present invention. In FIG. 1, 1 is C
PU, 2 is an O (output) port constituting an output device during processing, 3 is an abnormality detector for detecting an abnormality of the CPU, 4 is R
OM, 5 is an interrupt signal generator for automatically generating an interrupt signal periodically or irregularly, and 12 is a CP.
Signals (address bus, data bus, control bus) for U1 to communicate with O port 2 and ROM 4;
3 is an output of the O port, and 14 is an abnormality detection signal.

The ROM 4 stores a program to be executed by the CPU 1.
Arrives at CPU1, CPU1 proceeds to the next steps 1-4.
Is stored in such a manner that the processing of steps 1 to 4 is always completed before the next interrupt signal comes. That is, <Step 1> Set the output level of O port 2 to H level. <Step 2> A predetermined processing program is executed. <Step 3> Set the output of O port 2 to L level. <Step 4> End

That is, the output signal 13 of the O port 2 is programmed to be at the H level during the execution of the predetermined program, and at the L level after the end of the predetermined program. Abnormality detector 3
Performs an operation of latching the level of the output signal 13 of the O port 2 with the interrupt signal 11 and outputting the abnormality detection signal 14.

When the CPU 1 is operating normally and an interrupt signal 11 is received from the interrupt signal generator 5, since the previous processing has always been completed in accordance with the program stored in the ROM, the abnormality detector 3 latches the L level of the output level of the O port 2 and indicates that the abnormality detection signal is normal.

On the other hand, when the CPU 1 becomes abnormal during execution of the processing program, for example, when the CPU goes out of control and the interrupt signal 11 is received and the abnormal state continues, the output level of the O port 2 is at the H level. Therefore, the abnormality detector 3 latches the H level, and the abnormality detection signal 14 indicates that the CPU is abnormal. This abnormality detection signal is, for example, VT
In the case of the servo system of R, it is sent to the power supply block to turn off the power supply to the motor.

As described above, the abnormality of the CPU 1 can be detected. According to this embodiment, when a predetermined process is requested, it is checked whether or not the previous process has been completed, so that an abnormality of the CPU 1 can be detected even when the process is not a regular process. When used for periodic processing, there is no time delay corresponding to the time margin always provided in the WDT, so that the WDT can be used to detect an abnormality earlier than the CPU.

In the case of the above embodiment, the interrupt signal 1
In step 1, a predetermined processing program is started. Instead of an interrupt signal, a certain signal level is monitored by an I port constituting the processing request signal input device, and a predetermined processing is started by a change in the signal level. The processing program may be started by a simple interrupt signal. FIG. 2 shows a block diagram in this case. This embodiment is different from the embodiment of FIG. 1 in that an interrupt signal is not input to the CPU 1 but a processing request signal 31 from a processing request signal generator 20 for generating a substantial interrupt signal.
Are input to the I port 21, and the CPU 1 monitors the processing start signal 31.

Next, depending on the interrupt processing setting method of the CPU, when the next interrupt comes during execution of the previous interrupt processing, it is possible to accept and execute the next interrupt without waiting. FIG. 3 is a block diagram showing an embodiment in which the above setting is made. Here, reference numeral 22 denotes an I port constituting the signal input device during execution of processing, 23 denotes an O port for outputting an abnormality detection signal, and 24 denotes a ROM storing the interrupt processing program. In this case, ROM2
4 may store a program to be executed by the CPU as follows when the interrupt signal 11 from the interrupt signal generator 5 arrives at the CPU 1.

<Step 1> The output 13 from the I port 22 to the O port 2 is viewed. <Step 2> As a result, if the signal is at the H level, it is abnormal, so the abnormality detection signal 14 is output from the O port 23. If it is at the L level, it is normal and the process proceeds to the next step. <Step 3> The output level 13 of the O port 2 is set to the H level. <Step 4> Execute a predetermined program. <Step 5> Set the output of O port 2 to L level. <Step 6> End.

In the case of this embodiment, the I port 22, O
A storage device such as a memory or a register can be realized instead of the port 2. This embodiment is shown in the block diagram of FIG. In FIG. 4, the next processing program to be executed by the CPU 1 is stored in the ROM 26.

<Step 1> The contents of the memory 25 are checked. <Step 2> As a result, if the content during the execution of the predetermined processing is abnormal, the abnormality detection signal 14
Is output. If the predetermined process is completed, the process proceeds to the next because it is normal. <Step 3> The contents of the memory 23 are set to be in execution of a predetermined process. <Step 4> Execute a predetermined processing program. <Step 5> The contents of the memory 25 are terminated in a predetermined process. <Step 6> End.

In each of the above embodiments, the end of all processes is monitored. However, only some important processes in the processes are monitored, and only some important processes are completed by the next time. It is also possible to store a program that only needs to be stored in the ROM for execution.

[0022]

According to the present invention, when an interrupt signal is sent to the CPU, it is checked whether or not the previous interrupt processing has been completed, and if not, it is detected that the CPU is abnormal. As a result, it is possible to detect anomalies for irregular processing that was impossible with the WDT. Further, abnormality detection for periodic processing can be detected earlier than WDT.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a block diagram of a second embodiment of the present invention.

FIG. 3 is a block diagram of a third embodiment of the present invention.

FIG. 4 is a block diagram of a fourth embodiment of the present invention.

FIG. 5 is a block diagram of a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2 O port 3 CPU abnormality detector 4 ROM 5 Interrupt signal generator 20 Processing request signal generator 21 I port 53 WDT

──────────────────────────────────────────────────続 き Continuation of front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 11/28-11/36

Claims (4)

(57) [Claims] 1. A CPU, a storage device storing a predetermined program to be executed by the CPU, a processing request signal generator for generating a processing request signal for requesting the CPU to start a predetermined process, A process-in-progress signal output device that identifies when the process is being performed and when it is not and outputs a running signal; and when the process request signal comes or immediately before the CPU starts the predetermined process, The CPU detects an abnormality in the CPU while watching the execution signal , and outputs an abnormality detection signal.
That abnormality detector and a CPU abnormality detection apparatus comprising: a. 2. A control device based on the abnormality detection signal.
2. The CPU abnormality detection device according to claim 1, further comprising: a power supply device for stopping power supply of the CPU. 3. The CPU abnormality detection device according to claim 1, further comprising an I port for inputting the processing request signal. 4. A CPU, an interrupt signal generator for generating a signal for interrupting the CPU, and an interrupt signal from the interrupt signal generator,
, The interrupt processing by the subsequent interrupt signal is given priority over the interrupt processing by the previous interrupt signal.
A storage device storing a program to be executed by the PU;
U a signal during execution of a process that outputs a signal during execution of a signal, a signal input device during a process that receives a signal from the signal output device during a process, and an abnormal signal based on a signal input level of the signal input device during the process Signal output device for detecting an error and outputting an abnormality detection signal
Anomaly detection device.