JPS58166385A - Display memory access system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a RuskScan cathode lay tube (
This relates to an access method for a refresh memory C (hereinafter simply referred to as memory) of a CRT (hereinafter referred to as CRT). For more information, see Graphic Display, 4tK9
The Star Scan-Bitmap CRT has a graphics processing unit (hereinafter referred to as GP) for its drawing.
(referred to as U), the memory is accessed immediately. This invention provides a display memory and a display memory that efficiently performs this heating control.
It provides an access method.

In recent years, with the spread and advancement of information processing, Tsumbier's man-machine I
The original paper is based on the tendency to improve /F.

Conventionally, GP is stored in the memory of RuskScan display.
The method described below has been commonly used to store new data to be displayed, but as the amount of information to be handled increases and higher brightness is required, its shortcomings have become apparent.

[Conventional method 1] (Simple access method) The CRT side proposes and accesses the method 1, but the GP
When the U side performs access, the following method is used.

fD Access within the raster retrace time of the CRT.

@ Access at any time by prohibiting access on the CRT side.

When transferring/processing a large amount of data using this method, the disadvantage is that the access time of the GPU is reduced in Φ, and l& is extremely degraded. In addition, in O, normally the CRT side that is prohibited from accessing presses 1 to display during that time, but as the number of prohibited a, that is, the number of accesses to the GPU increases, the number of accesses to the ij side increases. Flickering appears, significantly deteriorating display quality.

[Conventional method 2] C-transparent method) The time slot of the memory access cycle is divided between the GPU side and the CRT side.
Both parties access the time slots allocated to them without each other being aware of the other. This will be explained with reference to the drawings.

FIG. 1 is a block diagram of a conventional trans-parent system. In this figure, 1 is a GPU, 2 is a CRT, S is a memory, and 4 is a multiplexer that switches access requests between the GPUI and the CRT 2.

FIG. 2 is a block diagram showing details of the multiplexer 4 of FIG. 1. In this figure, 1@, 11 is an AND circuit, 12
is an OR circuit, and 13 is an inverter. Signals A and B are memory access request signals from GPU1 and CRT2, respectively, and signal C switches signals A and B at a certain ratio, and is a control pulse with a period fixedly given at the time of design. be. The signal has the access right to the memory 3 switched as above.

The key point of this conventional method is that it is desirable that the access time of the shared memory 3 be considerably faster than the access time of the CRT 1. For example, if a twice-high-speed memory St is used, it is common that odd numbered slots are assigned as access rights to the GPU, and even numbered slots are assigned as access rights to the CRT2. In other words, CR
The T2111 can display a stable image regardless of GPU access, and if the access cycle on the GPU side is less than the memory cycle, the original access performance can be improved to 8.
Capacity down to 0% is guaranteed.

However, as mentioned above, there has been a demand for recent CRT display devices with large capacity, high resolution, and stable screens, that is, non-interlaced display.

For example, with the above settings, if you want to display at 60 frames/sec with an image quality of 1024 x 1024 dots and no interlace, the atase XX speed of CB'r2 is 1 s.
#si/9xp phase, 11a8/dot, memory capacity is 1! The speed of IIB varies depending on the access word length as follows.

16 bits/word, 51x1, ./1 = 811n8
/word, 32 bits/word, 11X3 wealth/2==
176a8/word, 64 pits)/waF, txxs
a/z=ss meaning-Ig/word.

In other words, if the memory 3 is fast, the access word width can be narrowed, but if the memory 3 is slow, the word width becomes wide. However, if all 3V of memory were to be implemented using large-capacity, high-speed memory, it would be extremely expensive.

The present invention has been made in view of the above points, and an object of the present invention is to provide a display memory access method that can be realized at low cost by efficiently accessing memory without increasing the memory capacity using low-speed messages. With the goal. This invention will be explained in detail below.

FIG. 3 is a block diagram showing an embodiment of the present invention, in which symbols 1 to 4, A# Bs D are the first! ! This is the same as that shown in 11. S is a first-in first-out buffer (hereinafter referred to as F), which receives future status monitoring signals 1. F is fed back to multiplexer 4, which is a switching circuit for memory access request signal system B.

FIG. 4 is a circuit example showing the details of the multiplexer 4 in FIG.
24 is a flip-flop which outputs an output when only one pin of signal M or B is 1 pin in the cruise route.
21 is an OR circuit which performs reset and setting upon receiving the E signal and F signal.

This invention is based on the fact that the CRT has dead time during which it does not access during the horizontal/111NIIlk period, and that the GPU
Even access is extremely intermittent, and in the conventional transparent method, even if GPUl does not access, CBTl accesses with a wide memory word width, so the access load on memory v3 is not uniform. This is done with a focus on

In other words, an intermediate KFIF@S between the memory 3 and the CRT 2 is provided, and 1 is normally KF+L while the GPUI is not accessing it.
% is full at 1 house and let me read ahead and G
In cycles where there is an access request for PUI, priority is granted to KGPUI, and CRT2 is given access to Pi.
The data in F@I is displayed and one page is held stably, and when the GPUl side is paused, F, F6 is displayed again.
m will continue until it is full. As the access frequency from GPUI increases, the number of constituent words N of F, F, and S increases.
Due to the relationship, there is a possibility that F, F, and S will become empty someday. Therefore, in this invention, FIF@! ! The number of data word stages stored in the memory is monitored, and when the number of remaining memory stages exceeds a certain limit, the priority is switched from the GPU1 side to the CRT2 side, and when F, F, and S become full. At that point, the switch is made from the CRT2 side to the GPU1 side.

I will explain it in a more different way. In the 1m3 diagram and Figure 4,
Maximum data transfer amount for memory 3 (reciprocal of cycle time)
is S-, and the required amount of data for CRT2 is 8. Then,
It is necessary that S, >L, and when the GPUI is idle, the memory 31% is used until the PIF is full at 61%.
Let C read ahead.

In this state, signal F is output from F, F, l, and the fourth
Diagram of flip-flop circuit! 4 is maintained in the set state. Therefore, when GPUI access begins, an access request signal is output.

CRT! If the time is not the same as the access request signal B from the side, access is granted unconditionally.

Even if it's the same time, there's no difference! ! , the output q of the flip 7p circuit 4 and the AND111820 [can be accessed preferentially].

GPUI access data amount is 81. Its duration t'
If tx is FiF,! #) Assuming that the number of stages is N, the following equation holds true.

8, e house, ≦8.・”* −fj H−tl + N−
1... (1) When this equation (1) becomes an equal sign, the access data amount 81 and the duration t occur, the PIF
, S or signal E is generated, and the 7-rip 7-rip circuit 24 in FIG. 4 is reset. Since the access request from the CRT1 side is always granted preferentially after dawn due to the AND circuit 11 in the pigeonhole where the signal and Shinmei Tomb were at the same time, the next (
2) Time t= K PIF, ! i becomes full again, signal 4#F is output, and control returns to the beginning and is repeated.

N-Electric t' 8m-8@)
...""""" (By controlling 11 or more, it is possible to give GPUIK high-speed access to the low-speed memory 3 while suppressing the access word length while outputting a stable screen to the CRT2. .In the actual design, G
The access frequency of PUl and the number of stages N of sFIF$11 are important parameters.

As explained in detail above, the present invention eliminates contention for access to the refresh Φ memory between a display device using a 791% scan type cathode array tube and a graphics processing unit using a first-in, first-out buffer. Use [When there is no access request from the graphics processing unit, read ahead and store the buffer memory.5&C, so use the slow refresh memory [1 item poor display line 5] I can do it. Also, I monitored the number of data words in the first-in/7th-out contest buffer and made sure that it did not fall below the specified number of stages.

It has the advantage of allowing trouble-free display.

[Brief explanation of the drawing]

Fig. 1 is a Gutsk diagram showing the conventional trans-parent system, Fig. 2 is a circuit diagram showing details of the multiplexer in Fig. 1, Fig. S is a Bootsk garden showing an embodiment of the present invention, and Fig. 14 is a diagram showing details of the multiplexer in FIG. In the figure, 1 is GPU, 2 is CRT, S is memory, 4i1v
loop+pvl+, HlPIFo, 20.21.22 is an AND circuit, 23 is an etus O exclusive off a road, 24 is a 7
Riphootpu path, I5 is an OR circuit.

Claims (1)

[Claims] (1) Regarding access to the display device using the RuskScan cathode tray tube and the graphite tape cinder unit and the glue fresh me 4ν, if there is no access request from the graphite tape transfer unit, 7 First in first out Φ buffer 7
The display method 41a access method is characterized in that the contents of the refresh memory are read in advance and stored. 7) First in, first out, buff 7, 7 Letssieme 4v look ahead is first in -
41. The display memory access method according to claim 1, wherein the number of stages of data words stored in the first-out buffer is monitored to ensure that the number of stages of data words does not fall below a predetermined number.