JPS5812556B2 - Digital direction measuring device display device - Google Patents
Digital direction measuring device display deviceInfo
- Publication number
- JPS5812556B2 JPS5812556B2 JP11799979A JP11799979A JPS5812556B2 JP S5812556 B2 JPS5812556 B2 JP S5812556B2 JP 11799979 A JP11799979 A JP 11799979A JP 11799979 A JP11799979 A JP 11799979A JP S5812556 B2 JPS5812556 B2 JP S5812556B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- digital signal
- time
- display device
- digital
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S3/00—Direction-finders for determining the direction from which infrasonic, sonic, ultrasonic, or electromagnetic waves, or particle emission, not having a directional significance, are being received
- G01S3/02—Direction-finders for determining the direction from which infrasonic, sonic, ultrasonic, or electromagnetic waves, or particle emission, not having a directional significance, are being received using radio waves
- G01S3/04—Details
- G01S3/046—Displays or indicators
Description
【発明の詳細な説明】
電波の到来する方位角をデイジタル量で読取るように(
一たデイジタル方位測定機において、到来する電波の強
度が弱い場f(1雑音成分のために表示されるテイジタ
ル量の特にF位の桁の値が頻繁に変動してその読取りが
困難になる。[Detailed Description of the Invention] In order to read the azimuth angle at which radio waves arrive as a digital quantity (
On the other hand, in a digital direction measuring device, if the intensity of the incoming radio wave is weak f(1), the displayed digital quantity, especially the F-digit value, fluctuates frequently due to the noise component, making it difficult to read it.
本発明にこのような場合に最も頻度の高い値を自動的に
表示して、その読取りを容易にしたものである。The present invention automatically displays the most frequent value in such a case, making it easier to read it.
第1図は本発明実施例のブロック図で、電波の到来方位
角が時々刻々測定されて、その方位角を示す例えば10
進3桁のテイジタル信号が端子Pに加えられる。FIG. 1 is a block diagram of an embodiment of the present invention, in which the arrival azimuth of radio waves is measured every moment, and the azimuth is indicated by, for example, 10
A three-digit digital signal is applied to terminal P.
デコーダBはこのテイジタル信号の最下位の桁を検出し
、その値0,1.2…9に応じて10個の出力端子0.
1,2…9のうち対応する端子から例えばパイレベルと
ローレベルよりなる2元信号の一方のパイレベルの信号
を送出する。Decoder B detects the least significant digit of this digital signal and outputs 10 output terminals 0, 1, 2, . . . , 9 according to its value.
For example, one pi level signal of a binary signal consisting of pi level and low level is sent out from the corresponding terminal among terminals 1, 2, . . . 9.
従って入力デイジタル信号かもL123であるとすると
出力端子3がパイレベルとなって他の端子はすべてロー
レベルを維持する。Therefore, if the input digital signal is also L123, the output terminal 3 becomes the pi level and all other terminals maintain the low level.
このような各出力端子の信号とクロノクパルス発生器K
から送出されるクロノクペルスとをそれぞれアンドゲー
トAo,A1……A9に加えて、その出力パルスを何れ
も同一の段数、例えば10段の計数器C0,C1……C
9でそれぞれ別個に計数する。The signal of each output terminal and the clock pulse generator K
The output pulses are applied to AND gates Ao, A1 .
Count each separately at 9.
この各計数器の桁上信号をオアゲート0に加えて、その
出力信号で全計数器C0,C1,……C9を同時にリセ
ットする。The carry signal of each counter is added to OR gate 0, and all counters C0, C1, . . . , C9 are simultaneously reset by the output signal.
すなわち計数器の1つが桁上信号を送出すると全計数器
かりセソトされて、再び各アンドゲートの出力ペルスを
計数し始める。That is, when one of the counters sends out a carry signal, all the counters are reset and start counting the output pulses of each AND gate again.
かつ上記オアゲートOの出力信号が記憶器Mを、駆動し
て、その時点における端子Pのテイジタル信号を記憶さ
せ、また表示器Dぱ該記憶器に記憶されている信号を常
時表示する。The output signal of the OR gate O drives the memory M to store the digital signal at the terminal P at that time, and the display D constantly displays the signal stored in the memory.
第2図は上述の装置の動作を説明するタイムチャートで
、pのように時々刻々変化する10進3桁のテイジタル
信号が第1図の端子Pに加えられる。FIG. 2 is a time chart illustrating the operation of the above-mentioned apparatus, in which a 3-digit decimal digital signal such as p that changes from time to time is applied to the terminal P shown in FIG.
例えば信号112ほ電波の到来方位が112度であるこ
とを示すもので、この信号が加えられるとテコーダBの
出力端子2がハイレベルとなる。For example, signal 112 indicates that the arrival direction of the radio wave is 112 degrees, and when this signal is added, the output terminal 2 of Tecoder B becomes high level.
またKはクロツクハルス発生器Kの出力パルスで、1ア
ノドゲートA0,A1 ……のうちデコーターBの出力
端子からパイレベルの信号を加えられているものだけが
このクロックパルスを通過させて計数器C。Also, K is the output pulse of the clock Hals generator K, and among the anode gates A0, A1..., only the one to which the pi level signal is applied from the output terminal of the decoder B passes this clock pulse to the counter C.
? C,…の1つに加える。すなわち例えば端子Pにテ
イジタル信号112が加えられているとき発生するクロ
ソクパルスは計数器C2に加えられてその計数値を1つ
増大させるもので、このため計数器C0,C1……C9
の計数値は第2図にC0,C1……C,で示したように
増大し、パルスk1で計器C1の計数値が10となって
桁上信号rが送出されると上記計数器がすべてリセット
される。? Add to one of C,... That is, for example, when the digital signal 112 is applied to the terminal P, the cross pulse that is generated is applied to the counter C2 and increases its count value by one, and therefore the counters C0, C1...C9
The count value increases as shown by C0, C1...C, in Fig. 2, and when the count value of the counter C1 becomes 10 at pulse k1 and the carry signal r is sent, all the counters mentioned above increase. will be reset.
かつ桁上信号で記憶器Mが駆動されてその時の入力デジ
タル信号例えば111が該記憶器に書き込まれ、その信
号に次に桁上信号rが送出されて記憶信号の書替えが行
われるまで表示器Dによって表示される。Then, the memory M is driven by the carry signal, and the input digital signal at that time, for example, 111, is written into the memory, and the display remains on until the next carry signal r is sent to that signal and the memory signal is rewritten. Displayed by D.
従って1つの桁上信号が送出されて各計数器が同時にリ
セットされたのち、計数値が最も早くフルスケールに達
した計数器に対応するデイジタル信号が記憶器に書き込
まれて、次の書込みまで表示される。Therefore, after one carry signal is sent and each counter is reset at the same time, the digital signal corresponding to the counter whose count value reached full scale earliest is written into the memory and displayed until the next write. be done.
かつ隣接する2つの桁上信号の間においては、後の桁上
信号を送出した計数器に対応するデイジタル信号が他の
信号より最も長時間に亘って端子Pに加えられていたこ
とは明白である。Moreover, between two adjacent carry signals, it is clear that the digital signal corresponding to the counter that sent out the latter carry signal was applied to terminal P for the longest time than the other signals. be.
すなわち本発明の装置は、入カデイジタル信号が雑音の
影響で頻繁に変動する場合において、自動的に決定され
る適当な期間中において、最も長時間に亘って加えられ
た信号を選出し、次の期間中これを表示するものである
。That is, when the input digital signal fluctuates frequently due to the influence of noise, the device of the present invention selects the signal that has been applied for the longest time during an automatically determined appropriate period, and selects the signal that has been applied for the longest time, and This will be displayed during the period.
このため真の電波到来方位である確率の最も高い数値が
長時間に亘って安定に表示され、その読取りを容易に行
い得る。Therefore, the numerical value with the highest probability of being the true radio wave arrival direction is stably displayed over a long period of time, and can be easily read.
しかも雑音成分が大きいために測定されたデイジタル信
号が広範囲に分布すると計数されるパルスが多数の計数
器に分配されて桁上信号の送出に長時間を有する。Moreover, since the noise component is large, when the measured digital signal is distributed over a wide range, the pulses to be counted are distributed to a large number of counters, and it takes a long time to send out the significant signal.
従って数値の選定に要する時間が自動的に増大して正確
な値の表示が行われる。Therefore, the time required to select a numerical value is automatically increased to ensure accurate value display.
第1図は本発明実施例のブロック図、第2図に第1図の
装置の動作を示1〜たタイムチャートである。
なお図において、Pぱ測定されたデイジタル信号の入力
端子、Bぱデコーダ、MU記憶器、Dは表示器、Kぱク
ロックパルス発生器、Ao,A1 ……A9Uアンドゲ
ート、co,C1…C,ぱ言セ狡器、0はオアゲートで
ある。FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a time chart showing the operation of the apparatus of FIG. 1. In the figure, P is the input terminal for the measured digital signal, B is the decoder, MU memory, D is the display, K is the clock pulse generator, Ao, A1...A9U and gate, co, C1...C, In other words, 0 is an or gate.
Claims (1)
えられて上記デイジタル信号の少なくとも下位の桁の値
に応じてそれぞれ異なる出力端子から信号を送出するテ
コーダと、クロソクパルスが加えられる毎に上記デコー
ダにおける各出力端子の信号をそれぞれ計数して1つの
計数器が桁上信号を送出すると全計数器が同時にリセッ
トされるように構成された同一段数を有する複数個の計
数器と、上記桁上信号が送出される毎に前記テイジタル
信号を記憶する記憶器と、上記記憶器に記憶された信号
を常時表示する表示器と、よりなることを特徴とするテ
イジタル方位測定機の表示装置。1. A decoder to which a digital signal corresponding to the measured azimuth angle at each time is applied and sends out signals from different output terminals according to at least the value of the lower digit of the digital signal, A plurality of counters having the same number of stages are configured so that when one counter sends a carry signal after counting the signals of each output terminal, all the counters are reset at the same time. A display device for a digital azimuth measuring instrument, comprising: a memory device that stores the digital signal each time it is sent; and a display device that constantly displays the signal stored in the memory device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11799979A JPS5812556B2 (en) | 1979-09-17 | 1979-09-17 | Digital direction measuring device display device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11799979A JPS5812556B2 (en) | 1979-09-17 | 1979-09-17 | Digital direction measuring device display device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5643569A JPS5643569A (en) | 1981-04-22 |
JPS5812556B2 true JPS5812556B2 (en) | 1983-03-09 |
Family
ID=14725530
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11799979A Expired JPS5812556B2 (en) | 1979-09-17 | 1979-09-17 | Digital direction measuring device display device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5812556B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60204572A (en) * | 1984-03-29 | 1985-10-16 | Sadami Ito | Sheetlike material to be stuck |
JPS6348784B2 (en) * | 1984-09-06 | 1988-09-30 | Sadami Ito | |
JPS6348783B2 (en) * | 1984-04-09 | 1988-09-30 | Sadami Ito |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5895272A (en) * | 1981-12-02 | 1983-06-06 | Nippon Telegr & Teleph Corp <Ntt> | Controlling device for antenna directivity |
JPS6288784A (en) * | 1985-10-15 | 1987-04-23 | Hitachi Cable Ltd | Tape winding method and its device |
-
1979
- 1979-09-17 JP JP11799979A patent/JPS5812556B2/en not_active Expired
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60204572A (en) * | 1984-03-29 | 1985-10-16 | Sadami Ito | Sheetlike material to be stuck |
JPS6348783B2 (en) * | 1984-04-09 | 1988-09-30 | Sadami Ito | |
JPS6348784B2 (en) * | 1984-09-06 | 1988-09-30 | Sadami Ito |
Also Published As
Publication number | Publication date |
---|---|
JPS5643569A (en) | 1981-04-22 |
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