SU1524013A1 - Device for analyzing the shape of frequency signal envelope - Google Patents

Abstract

The invention relates to information-measuring and computing technology and can be used to analyze the form of deterministic and random pulsed and frequency-modulated signals. The purpose of the invention is to expand the functionality of the device by organizing an additional mode of detailed analysis of the fragments of the signal envelope displayed in real time. For this, the device organizes an additional mode of storing and displaying the sums of a predetermined number of samples of the signal envelope. For this purpose, an adder 22, registers 23, 24, a storage unit 25, switches 26, 27, delay elements 28, 29, an AND element 30, a dial-in field 31 are entered into the device. In addition, the device contains a pulse generator 1, ADC 2, a counter 3 read addresses, write address counter 4, registers 5, 6, compare unit 7, switch 8, storage unit 9, shaper 10 short pulses, decoder 11 zero, divider 12, triggers 13, 14, And 15, 16 elements, shaper 17 short pulses, elements 18, 19 delay, DAC 20, indicator unit 21. 1 Il.

Description

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analysis of fragments of the signal envelope displayed in real time. For this, the device organizes an additional mode of storing and displaying the sums of a predetermined number of samples of the signal envelope. Adding this to the device is the adder 22, the registers 23, 2A, the apocommunications unit 25, the switches 26, 27, the delay elements 28, 29, the element 30, the dial field 31. In addition, the device contains a generator of I pulses, MS 2 read address counter 3, write address counter A, registers 5, 6, comparison block 7, switch 8, storage unit 9, shaper 10 short pulses, decoder 11 zero, divider 12, triggers 13, 14, And 15, 16 elements, shaper 17 short pulses, delay elements 18, 19, DAC 20, indicator unit 21. 1 sludge.

The invention relates to information-measuring and computing technology and can be used to analyze the form of deterministic and random pulsed and frequency-modulated signals.

The purpose of the invention is to expand the functional capabilities of the device by organizing an additional mode of detailed analysis of the fragments of the signal envelope displayed in real time.

The drawing shows a block diagram of the device.

The device contains a pulse generator 1, an analog-digital converter 2, read address counters 3 and write 4, first 5 and second 6 registers, comparison unit 7, first switch 8, memory-block 9, first short pulse shaper 10, decoder 11 zero, divider 12 first 13 and second 14 triggers, first 15 and second 16 elements And, second shaper 17 short pulses, first 18 and second 19 delay elements, digital-to-analog converter 20, indicator unit 21, adder 22, third 23 and fourth 24 registers ; an additional storage unit 25, second 26 and third 27 switches, third 28 and fourth 29 delay elements, third And 30 element, dial field 31, the output of the pulse generator 1 is connected to the left input of the analog-to-digital converter 2 and the read address counter 3, informational the input of the device is the second input of the analog-digital converter 2, the output of which through the first register 5 is

five

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edr1nen with the first input of the second register 6 and the first input of the comparison unit 7, the output of which is connected to the first input of the second element 16, the output of the second register 6 is connected to the second input of the comparison unit 7, the first input of the storage unit 9 and the first input of the adder 22, the output of which through the third register 23 is connected to the fourth register 24, the output of which is connected to the second input of the adder 22 and the first input of the block 25, the output of the counter 3 of the read address is connected to the input of the decoder 11 zero, to the first input of the first switch 8 and the first input the second switch 26, as well as through the divider 12 is connected to the first inputs of the write address counter 4 and the first trigger 13, the record address counter 4 is connected to the second input of the second trigger 14 by the third output, the second output to the second input of the first switch 8 And 30, the second output to the third input of the switch 8 and the second input of the second switch 26, the output of the second trigger 14 is connected to the second inputs of the divider 12 and the write address counter 4, the output of the dial field 31 is connected to the fifth input of the first switch 8, The outputs of the first and second switches 8 and 26 are connected respectively to the second inputs — the address buses of the storage unit 9 and the additional storage unit 25, whose outputs are connected respectively to the second and first inputs of the third switch 27, whose output is connected to the second input of the indicator unit through the digital-to-analog converter 20 21, you515

the zero decoder 11 is connected to the input of the first driver 10 pulses, with the fourth input of the first switch 8 and the third input of the second switch 26, with the first input of the indicator unit 21 and the input of the second driver 17 of the pulses, the output of the first driver 10 of the pulses is connected to the second input of the first register 5 and the third input of the analog-to-digital converter 2, and through the second input of the first trigger 13 to the first input of the first element AND i5, the output of the second driver 17 pulses is connected via the second input of the second element And 16 with the third input of the second register 6, and through the second delay element 19 - with the second input of the first element And 15, the output of the first element And 15 is connected to the third input of the adder 22, with the second input of the third register 23, and through the third delay element 28 - with the second input of the fourth register 24 and the first input of the third element And 30 whose output is connected to the third input of the block 25 and through the fourth delay element 29 is connected to the third input of the fourth register 24, the third input of the storage unit 9 is connected to the outputs of the first element 15, through p The first delay element 18 with the second input of the second register 6, the control inputs of the device are the Start inputs - the first input of the second flip-flop 14, which defines the beginning of the recording of information (local maxima and average values) in the storage unit 9 and the additional

storage unit 25, Mode — third input of the third switch 27, determining the mode of reading information from the additional storage unit 25 or from the array of the storage unit 9 and output to the display unit 21 of the entire envelope or its fragment and the Segment number — inputs of the dial field 31, defining Selection of one or another array of the storage unit 9 by feeding the higher bits of the address code to the fifth input of the first switch 8 in the readout direction.

The proposed device can operate in two modes x: the first corresponds to the display on the indicator of the frequency-modulated signal envelope for a period of time T, and the second

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It corresponds to the display on the indicator of a fragment of the bend (it has a frequency-modulated signal during the time T / n, where n is the number of fragments, i.e. the second mode is used to specify the corresponding fragment.

The mode is selected by the command of the Mode supplied to the third switch 27, while if the second mode is selected, then one of the n fragments is selected by installing the keyboard with the fragment number on the dial field 31.

The device in cyclic mode works as follows.

In the initial state, the second trigger 14 is set by the overflow signal of the counter 4 of the write address to the state prohibiting the operation of the divider 12 and the counter 4 of the write address. The first trigger 13, in turn, is in a state prohibiting the recording of information in the storage unit 9 and in the additional storage unit 25, i.e. locks the recording mode. Thus, in the initial state, only the cyclic reading of information from the storage 9 or additional 25 storage blocks occurs, the selection of one of which is prevented by applying the Mode command to the third switch 27.

When the second trigger 14 is switched by the command Start, the count of the divider 12 and the count 4 address of the entry are resolved, which leads to the resolution of the calculation of code equivalent X. (where i is the instantaneous value sequence number) of the instantaneous amplitudes of the frequency-modulated or non-periodic pulse of the analog signal to digital converter 2, calculating local maximum values of Y max X: (where j j

the sequence number of the local maximum value, and t (the time interval for which the local maximum value is determined) to the first and second registers 5 and 6, block 7 of the comparison and the second element AND 16 and calculate

laziness averaged values of Z T Y./m

Tgde K is the sequence number of the averaged value, m is the constant number of summations) adder 22, the third 23 and fourth 24 registers with a sequence of local maximum values Y for the time interval / IV g storing unit 9, and the average values of Z for the time interval , „„ In the additional application

passing block 25.

The local maximum values of the input signal are computed over the time interval t using an analog-digital converter 2, the first 5 and second 6 registers, comparison unit 7, and the second element 16. And for processing the frequency-modulated signal, the algorithm for finding the maximum of the instantaneous values of the input signal during the recording time interval ut. The code equivalents Xj of the instantaneous amplitudes of the input signal obtained from the output of the analog-digital converter 2 are recorded in the first register 5, after which its contents are compared with the contents of the second register 6 in the comparison unit 7. If the code recorded in the first register 5 is greater than the code in the second register 6, it is rewritten in the second register 6. Otherwise, the previous value remains in register 6. Thus, by the end of the interval t-j in the second register 6 is the value of the local maximum Y: input signal for the time interval. The second element AND 16 performs the function of a building element for a write pulse to the second register 6 from the output of the second shaper 17 short pulses. Before starting to calculate the next local maximum Yj, the second register is brought to the zero state by the input signal of the first element AND 1 5 delayed on the first delay element 18.

The calculation of the average value of Z1 over the time interval m-; it3on is carried out using the adder 22, the third 23 and the fourth 24 registers, the third delay element 28, the third element AND 30, and the counter 4 of the write address. The local maximum value of Y for the time interval stored in the second register 6 and the value contained in the fourth register 24 is fed to the input of the adder 22, the sum value is rewritten n the third register 3 and with a delay:. rewrite

in fourth register 24. The third element AND 30 performs the control of the number of items in the calculation of the average value of Z over a time interval,. The third element And 30 determines when all the lower bits at the output of the address of the record 4 are in the active level state. The active level at the output of the third element And 30 is formed in the case

if the sum of V is accumulated, and as an equal signal to write comes

to the input of the additional storage unit 25, the same signal, delayed by the fourth delay element 22, resets the fourth register to the zero state before the start

calculating the next average

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Z values. The sum of Y.Y. counts

J accumulated if it consists of m

terms. To determine the averaged value, i.e. average arithmetn

7 Y./m, from the output of even-

Only one of the higher bits is fed to the first register 24 at the first input of the storage unit 25.

The mode of sequential recording of information in the cells of the memorization unit 9 and the additional storage unit 25 and cyclic interrogation of the cells (read mode) is performed using seven main blocks: dial pad 31, read address counters 3 and write 4, divider 12, first 8 and second 26 address switches, the third switch 27. Divider 12 provides the necessary write speed, switches 8 and 26 are connected to the address buses of the storage unit 9 and the additional storage unit 25, address and write address codes from the outputs of the respective counters. The connection of the write address counter 4 is performed at the zero address of the counter of the read address 3 decoded using the decoder II zero, which allows to simplify the generation of control signals and does not affect the display quality, since the indicator unit 21 is at this time in the ray-return mode (i.e. beam quenching). Writing to the additional storage unit 25 is made as the amount is accumulated and takes place with a delay formed on the third

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the delay element 28, iiruijie, is stored in the storage unit 9. Information can be read from either the additional storage unit 25 or from the storage unit 9 array The selection of the storage unit 9 or 25 and the selection of the storage unit array 9 are made by setting the storage box 31 to the array. 9 is made with the help of the Number of the segment key. In this case, the high-order bits of the address code from the dial-up field 31 in parallel with the lower bits of the counter 3 read addresses through the switch 8, the addresses are connected to the address The third bus of the storage unit 9, the Third switch 27 connects the information outputs of the storage unit 9. or the additional storage unit 25 to the python analog converter 20, which is used to generate the analog signal for the indicator unit 21. The switch 27 is controlled by the Mode key.

All processes in the device are synchronized by the frequency of the pulse generator 1, and for obtaining control signals, shapers 10 and 17 short pulses are used, which operate respectively on the falling and leading edges of the output signal of the decoder II zero. The control and synchronization processes in the device are distributed in time as follows.

At the time of setting the zero clock of the counter 3 of the read address at the output of the second short pulse pulse generator 17, a pulse is formed to gate the second element 16, which, if necessary, records the local maximum Y value in the second register 6. It is also delayed by the second delay element 19 will enter the input of the first element 15 and if the first trigger 13 is in the single state, a signal will be generated at the output, which is fed to the storage unit as the control signal a 9, to the input of the adder 22 and the third register 23, through the first delay element 18 - to the input of the second register 6, and through the third delay element 28 - to the third element I 30 and to the input of the fourth register 24. When the transmitting signal is applied to the input of the storage unit 9 pro3

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It is necessary to rewrite the computed local maximal Y value and the second register 6 into the memory (third block 9, and then with the delay formed by the first delay element 18, reset the second register 6 to the zero state. When the control signal is applied to the input of the adder 22 and the input the third register 23, and through the third element 28 of the input delay of the fourth register 24 will sum up the contents of the second and fourth registers 6 and 24, overwriting the amount received in the third register 23 with some delay formed by the third email ment 28 delays the fourth register 24. The control signal on the input of the third AND gate 30 organizes summand amount by x amount in the case of

m

if the sum is X y. accumulated

A control signal is fed to an additional memory unit 1, block 25, which will be used to record the averaged h) z-step Z., during the time interval radt.,

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from the fourth register 24 to the additional storage unit 25, after which the control signal delayed by the fourth delay element 29 from the output of the third element I 30 will reset the fourth register 24 to the zero state.

The first trigger 13 is set to one state when the address of the record is changed to the memory unit 9, since its counting input is combined with the counting input of the counter 4 of the write address. The first trigger 13 is reset, the converted input information is written to the first register 5, and the analog-digital converter 2 is synchronized at the moment of the end of the zero clock of the counter 3 of the read address by pulse from the output of the first driver 10 short pulses.

Claims (1)

At the end of the recording, the counter 4 of the write address will overflow and the second trigger 14 returns to its original state, which was described earlier. The recording mode is blocked, and the cyclic reading of information continues, while the display unit 21 will remain the image of the recorded information. Invention Formula A device for analyzing the shape of the envelope of a frequency signal, containing 152 analog-digital pulse generator transducer, read address counter, write address counter, first and second registers, compare unit, first address switch, storage unit, first and second short pulse drivers, decoder zero, divider, first and second triggers, first and second elements, And, the first and second delay elements, a digital-to-analog converter and an indicator unit; the output of the pulse generator is connected to the input of the read address counter and the first input of the analog-to-digital converter, whose second input is information input device, and the output is connected to the first input of the first register, the output of which is connected to the first inputs of the comparison unit and the second register, the output of the second register is connected to the second input of the comparison unit and the first input of the storage unit, the second input of the storage unit is connected to the output of the first address switch whose first input is connected to the input of the decoder zero, the first input of the divider and the output of the read address counter, and the second and third inputs of the first address switch are connected according to At the first and second outputs of the write address counter, the first input of which is connected to the output of the divider and the first input of the first trigger, the output of the zero decoder is connected to the fourth input of the first switch, the first input of the indicator block and the inputs of the first and second shapers of short pulses, the output of the first short pulse shaper is connected to the second input of the first register, the third input of the analog-digital converter and the second input of the first trigger, the output of which is connected to the first input of the first And, the second input of the first element And is connected to the output of the second delay element, and the output is connected to the third input of the storage unit and through the first delay element to the second input of the second register, which has a third input (connected to the output of the second element And, the first input of the second element I is connected to the output of the comparison unit, and the second input is connected to the input of the ical delay element and the output of the short shaper of short imp gypsum 0 5 Q f e Q, five 12 the first input of the second trigger is the device Start input, the second input of the second trigger is connected to the third output of the write address counter, and the output to the second input of the write address counter and the second divider input, the output of the digital-to-analog converter is connected to the second input of the indicator unit, the output of the storage unit is Output to the device storage device, characterized in that, in order to expand the functionality of the device by organizing an additional mode of detailed analysis of envelope fragments with a real-time signal is sent to it in the adder, the third and fourth registers, the additional storage unit, the second and third switches, the third and fourth delay elements, the third And element and the composing field, with the output of the second register through the adder, the third the register and the fourth register, which are connected in series through their first inputs, are connected to the second input of the adder and the first input of the additional storage unit, the second bypass of which is connected to the output of the second switch, The first input is connected to the output of the read address counter, the second input is connected to the second output of the write address counter, the third input is connected to the output of the decoder zero, and the output of the additional storage unit is connected to the first input of the third switch, the output of which is connected to the digital-to-analog converter The second input of the third switch is connected to the output of the storage unit, and the third input is the input device mode, the output of the first element is connected to the third input of the adder, the second input is tert its register and through the third delay element with the second input of the fourth register and with the first input of the third element I, the output of which is connected to the third input of the additional storage unit and the input of the fourth delay element whose output is connected to the third input of the fourth register, the first output of the write address counter with the second input of the third element And, the fifth input of the first switch is connected to the output of the racks on the floor, the ports of which are the inputs of the device segment.