JPS58125472U - Jitter suppression device for teletext receivers - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

Fig. 1 shows a block diagram showing the principle of a teletext receiver, Fig. 2 shows a block diagram of a clock generation circuit in the above, and Fig. 3 shows a jitter suppression device for a character transceiver according to the present invention. A block diagram of a clock generation circuit which is a main part of one embodiment is shown, and FIG. 4 is an explanatory diagram for explaining the operation of the same embodiment. 3: 20H/4QH detection circuit, 4. STX detection circuit,
5: Clock generation circuit, 6: Color carrier regeneration circuit, 11:
Input gate, 12: Program matching circuit, 13: Scanning line matching circuit, 14: Buffer memory, 15: Clock gate, 1
6: Rewrite gate, 17: Main memory, 18: Clock gate, 51: 8 multiplier circuit, 5□: Frequency divider circuit, 53 NIO gate circuit. 1/゛Figure 3

Claims (1)

[Scope of utility model registration request] A burst signal in a television video signal is used in a teletext receiver that reproduces information such as characters and graphics inserted in the vertical retrace period of a television video signal in response to clock pulses and displays it on the television screen. Multiplying/dividing means generates clock pulses by multiplying the reproduced color subcarrier signal by a predetermined number (including fractions) based on Clock pulse phase control means for controlling the phase of the clock pulse based on both the IJ4° signal responsive to the horizontal synchronizing signal corresponding to the display period for displaying the image and the STX signal included in the character signal. A jitter suppression device for a teletext receiver, comprising: