JPH0334791Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a CRT display device that displays pattern images such as characters and graphics.

Conventional CRT display devices that display pattern images such as characters and graphics are the first
As shown in the figure, the horizontal and vertical deflection sections and the display signal generation circuit were synchronized by independent synchronization signal generation circuits.

In FIG. 1, a horizontal synchronization signal generated from a synchronization signal generation circuit 11 synchronizes a horizontal oscillation/amplification section 12. The horizontal output section 13 receives this synchronized horizontal oscillation output and supplies a sawtooth horizontal deflection current to the horizontal deflection coil 14. Further, the vertical synchronization signal generated from the synchronization signal generation circuit 11 synchronizes the vertical oscillation/amplification section 15. The vertical output section 16 is
In response to this synchronized vertical oscillation output, a sawtooth vertical deflection current is supplied to the vertical deflection coil 17.

The horizontal and vertical synchronizing signals generated from the synchronizing signal generating circuit 11 are further supplied to a display signal generating circuit 18. The display signal generation circuit 18 sequentially outputs display pattern signals in a format similar to the video signal in television in synchronization with the horizontal and vertical synchronizing signals.

This pattern signal is sent to the CRT in the video amplification section 19.
Amplified to a level that drives 10, CRT
Horizontal and vertical deflection coils 14, 17 in 10
A predetermined pattern image is emitted and displayed on the display surface of the CRT 10 in accordance with the scanning of the electron beam by the CRT 10.

Although FIG. 1 has been explained in the case of a monochrome CRT display device, the same applies to the case of a color CRT display device.

Displaying the conventional pattern image like this
CRT display devices require a special synchronization signal generation circuit for generating horizontal and vertical synchronization signals in order to synchronize the horizontal and vertical deflection sections with the display signal generation circuit. As a result, CRT display devices became more complex and expensive, and space was required for the synchronization signal generation circuit, which hindered miniaturization of the device.

The present invention was made to improve the above-mentioned problems in conventional CRT display devices that use pattern images. By extracting the timing pulse from the display signal generating circuit and using it to synchronize the display signal generating circuit, it is possible to synchronize the pattern signals from the horizontal and vertical deflection sections and the display signal generating circuit without providing a special synchronizing signal generating circuit. The purpose of the present invention is to provide a CRT display device that is simple in configuration and low in cost.

Hereinafter, the present invention will be explained in detail based on an embodiment shown in FIGS. 2 to 6.

FIG. 2 is a block diagram of an embodiment of the CRT display device of the present invention.

In Fig. 2, 21 is a horizontal oscillation circuit that oscillates at a frequency o _H ≒ 15.75 KHz, and generates a horizontal oscillation signal HS with a period of 1H (1H = 1/o _H seconds), for example, as shown in Fig. 6 a. .

This horizontal oscillation signal HS is amplified by the horizontal amplifier circuit 22 and applied to the horizontal output circuit 23. The horizontal output circuit 23 receives the horizontal oscillation signal HS and supplies a sawtooth horizontal deflection current to the horizontal deflection coil 24.

25 is a vertical oscillation circuit that oscillates at a frequency o _V ≒ 60 Hz, for example, as shown in Figure 6c, with a period of 1 V.
Generates a vertical oscillation signal VS of (1V = 1/o _V seconds). This vertical oscillation signal VS is transmitted to the vertical amplifier circuit 26.
The signal is amplified and applied to the vertical output circuit 27. The vertical output circuit 27 receives the vertical oscillation signal VS and supplies a sawtooth vertical deflection current to the vertical deflection coil 28.

The horizontal oscillation circuit, the horizontal amplifier circuit, and the horizontal output circuit constitute a horizontal deflection section, and the vertical oscillation circuit, the vertical amplifier circuit, and the vertical output circuit constitute a vertical deflection section.

29 is a horizontal timing pulse generation circuit which receives the horizontal oscillation signal HS from the horizontal oscillation circuit 21, shapes the waveform of this signal, and generates a period of 1H as shown in FIG. 6b.
The timing pulse HT is generated. This horizontal timing pulse HT is supplied to the display signal generation circuit 36 as a signal corresponding to a horizontal synchronization signal.

30 is a vertical timing pulse generation circuit which receives the vertical oscillation signal VS from the vertical oscillation circuit 25, shapes its waveform, and generates a vertical timing pulse VT with a period of 1V as shown in FIG. 6d. This vertical timing pulse VT is supplied to the display signal generation circuit 36 as a signal corresponding to a vertical synchronization signal. The display signal generation circuit 36 uses the vertical timing pulse VT to set the vertical writing timing of the display pattern, that is, the page break timing, and the horizontal timing pulse HT to set the horizontal writing timing, that is, the line feed timing.

FIG. 3 shows a block diagram of the configuration of the signal generation circuit 36. The display controller 31 writes the pattern data to be displayed into a predetermined address of the RAM 32, and also supplies a control signal for moving the horizontal display to the next line to the memory address setting circuit 35 using the horizontal timing pulse HT. Further vertical timing pulse
A control signal for moving to the next frame (screen) is supplied to the memory address setting circuit 35 by the VT.

The oscillator circuit 33 generates a clock (CK) for sending out a display signal and outputs a clock (CK) to the shift register 3.
At the same time, this clock CK is also supplied to the memory address setting circuit 35. clock
The frequency of CK is determined by the width of one display dot.

The memory address setting circuit 35 has display pattern data written corresponding to the display location on the screen.
Specify the RAM32 address.

The shift register 34 performs an operation of converting parallel pattern data read from the RAM 32 into a serial pattern signal. That is, the pattern data of the RAM 32 addressed by the address setting circuit 35 is loaded in parallel into the shift register 34, and output as a serial pattern signal by the clock CK from the oscillation circuit 33.

In this way, the display signal generation circuit 3
From 6 onwards, the horizontal and timing pulses HT and
The VT outputs a pattern signal to the video amplification circuit 37 in which the writing timing of the displayed pattern image in the horizontal and vertical directions is made constant.

The video amplification circuit 37 amplifies the pattern signal to the CRT drive level and supplies it to the CRT 38.

FIG. 4 shows an example of a display pattern displayed by the CRT display device of the present invention, where a indicates the display pattern screen and b indicates the video signal at that time, that is, the shift register of the display signal generation circuit 36. The pattern signal output from 34 is shown. As mentioned above, the scan start point (left end) of each horizontal scan line is the horizontal timing pulse HT.
The scanning start point (upper end) of the screen is defined by the vertical timing pulse VT.

In this example, the horizontal and vertical timing pulses
The horizontal oscillation circuit 21 generates signals for HT and VT generation.
and vertical oscillation circuit 25, these are
As shown by dotted lines in FIG.
In addition to the output end, the signal may be taken out from a point where it is easy to take out in consideration of the signal level and signal waveform.

Further, the CRT display device is not limited to monochrome, but can also be applied to a display device using a color CRT.

In the present invention, since the horizontal oscillation circuit 21 and the vertical oscillation circuit 25 are free running asynchronously with each other, assuming that horizontal scanning is started when the vertical timing pulse VT reaches the L level, as shown in FIG. As shown in , it takes up to 1H to start horizontal scanning.
This results in a time error of On the other hand, since the display data for pattern display is superimposed on the horizontal timing pulse a certain number of pulses after the standard horizontal timing pulse HTo (in the figure, after 3 pulses have been counted), the display starts at the maximum vertical direction. There may be cases where there is a shift of 1H line, and these appear as flickering up and down on the display screen.

However, this level of vertical flickering
Since it is not distinguishable on the display screen, it does not pose any practical problem.

As explained above, according to the present invention, the horizontal and vertical deflection sections take out the horizontal and vertical timing pulse signals and display on the CRT using these timing pulse signals. Since the display pattern signal can be loaded in timing with the run deflection, there is no need to provide separate external circuits for generating horizontal and vertical synchronizing signals, simplifying the configuration of the CRT data device and reducing costs. can be reduced.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional CRT display device, Fig. 2 is a block diagram of a CRT display device of the present invention, Fig. 3 is a block diagram of a display signal generation circuit used in Fig. 2, and Fig. 4 is a block diagram of a CRT display device of the present invention.
6 to 6 show operating waveform diagrams of FIG. 2. 21...Horizontal oscillation circuit, 22...Horizontal amplifier circuit, 23...Horizontal output circuit, 24...Horizontal deflection coil, 25...Vertical oscillation circuit, 26...Vertical amplifier circuit, 27...Vertical output circuit, 28 ... Vertical deflection coil, 29 ... Horizontal timing pulse generation circuit, 30 ... Vertical timing pulse generation circuit, 3
1...Display controller, 32...
RAM, 33...Oscillation circuit, 34...Shift register, 35...Memory address setting circuit, 36...
...Display signal generation circuit, 37...Video amplification circuit, 38...CRT.

Claims (1)

[Scope of utility model registration request] a horizontal deflection section including a horizontal deflection circuit, a horizontal amplification circuit, and a horizontal output circuit; a vertical deflection section including a vertical deflection circuit, a vertical amplification circuit, and a vertical output circuit; a horizontal timing pulse generation circuit that generates a synchronized horizontal timing pulse; a vertical timing pulse generation circuit that generates a vertical timing pulse that is synchronized with vertical deflection using a signal taken out from the vertical deflection section; and the horizontal timing pulse and the vertical timing pulse. 1. A CRT display device, comprising: a display signal generation circuit which outputs a pattern signal for display in accordance with the horizontal and vertical deflection in accordance with the horizontal and vertical deflection, thereby eliminating the need for independent horizontal and vertical synchronization signal generation circuits.