JPS5760412A - Monitoring method of programmable logic controller of random acess discrete address diagram system - Google Patents

Monitoring method of programmable logic controller of random acess discrete address diagram system

Info

Publication number
JPS5760412A
JPS5760412A JP55135652A JP13565280A JPS5760412A JP S5760412 A JPS5760412 A JP S5760412A JP 55135652 A JP55135652 A JP 55135652A JP 13565280 A JP13565280 A JP 13565280A JP S5760412 A JPS5760412 A JP S5760412A
Authority
JP
Japan
Prior art keywords
instruction
monitor
output
transfer part
display
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55135652A
Other languages
Japanese (ja)
Inventor
Masaaki Hotta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Tateisi Electronics Co
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tateisi Electronics Co, Omron Tateisi Electronics Co filed Critical Tateisi Electronics Co
Priority to JP55135652A priority Critical patent/JPS5760412A/en
Publication of JPS5760412A publication Critical patent/JPS5760412A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
    • G05B19/058—Safety, monitoring
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

PURPOSE:To read an execution state of IL from a local display, too, by adding a state of an output inhibiting signal by an interlock IL instruction, to input/output staes by a logical operation result in case when the instruction is executed, and executing its monitor display. CONSTITUTION:A monitor device 2 inputs a program address range for specifying an instruction group to be monitored by a keyboard 8, and transmits its data to a transfer part 5 of a controller CTL1 from a transfer part 10. The CTL1 receives it, stores a monitor data regarding an instruction being within a program address range designated when the instruction is executed, in buffer memory of the transfer part 5, and transfers the monitor data to the transfer part 10 without discontinuing the operation of a main control part 3. The monitor data consists of a logical operation result in case when the instruction is executed, and a status data by an output inhibiting signal controlled by an IL instruction, and the device 2 decodes the monitor data by a display control part 7, and display an RADA diagram obtained by adding a state of the output inhibiting signal to input/output states, on a CRT6.
JP55135652A 1980-09-29 1980-09-29 Monitoring method of programmable logic controller of random acess discrete address diagram system Pending JPS5760412A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55135652A JPS5760412A (en) 1980-09-29 1980-09-29 Monitoring method of programmable logic controller of random acess discrete address diagram system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55135652A JPS5760412A (en) 1980-09-29 1980-09-29 Monitoring method of programmable logic controller of random acess discrete address diagram system

Publications (1)

Publication Number Publication Date
JPS5760412A true JPS5760412A (en) 1982-04-12

Family

ID=15156790

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55135652A Pending JPS5760412A (en) 1980-09-29 1980-09-29 Monitoring method of programmable logic controller of random acess discrete address diagram system

Country Status (1)

Country Link
JP (1) JPS5760412A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1984003964A1 (en) * 1983-04-06 1984-10-11 Fanuc Ltd Alarm display method for programmable controller
EP0148951A1 (en) * 1983-05-09 1985-07-24 Fanuc Ltd. System for checking abnormality in programmable controller
JPS6121507A (en) * 1984-07-09 1986-01-30 Omron Tateisi Electronics Co Monitor device of programmable controller

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1984003964A1 (en) * 1983-04-06 1984-10-11 Fanuc Ltd Alarm display method for programmable controller
EP0148951A1 (en) * 1983-05-09 1985-07-24 Fanuc Ltd. System for checking abnormality in programmable controller
JPS6121507A (en) * 1984-07-09 1986-01-30 Omron Tateisi Electronics Co Monitor device of programmable controller

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