JPS5758444A - Clock extracting system in dipulse code composite circuit - Google Patents

Clock extracting system in dipulse code composite circuit

Info

Publication number
JPS5758444A
JPS5758444A JP55133790A JP13379080A JPS5758444A JP S5758444 A JPS5758444 A JP S5758444A JP 55133790 A JP55133790 A JP 55133790A JP 13379080 A JP13379080 A JP 13379080A JP S5758444 A JPS5758444 A JP S5758444A
Authority
JP
Japan
Prior art keywords
pulse train
dipulse
output
circuit
train
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55133790A
Other languages
Japanese (ja)
Inventor
Koji Nishizaki
Masanori Arai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55133790A priority Critical patent/JPS5758444A/en
Publication of JPS5758444A publication Critical patent/JPS5758444A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4904—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using self-synchronising codes, e.g. split-phase codes

Abstract

PURPOSE:To obtain a dipulse train equal to clocks at the input terminal of a timing extracting circuit only by adding a simple logical circuit. CONSTITUTION:An inputted dipulse code train (a) goes to a pulse train (b) through being delayed at a 1/2-period delay circuit 9. When logical product and negative logical sum are taken for the pulse trains (a) and (b), a logical product output (c) indicates the phase of front end of a time slot corresponding to ''1'' of an NRZ code and a negative logical sum output (d) indicates the phase at rear edge. Thus, when the pulse train (c) is inputted to a set terminal of a set/reset circuit 10 and to the reset terminal for the pulse train (d), respecively an output (e) is a pulse train indicating the location of the dipulse code corresponding to ''1'' of the NRZ data. When this pulse train (e) and the input (a) are taken for exclusive logical sum, the dipulse code ''10'' corresponding to ''1'' of the NRZ data is inverted, and an output (f) is a pulse train equal to a f0 clodk. This pulse train (f) is inputted to a timing extracting circuit 11 to reproduce a complete f0 clock.
JP55133790A 1980-09-26 1980-09-26 Clock extracting system in dipulse code composite circuit Pending JPS5758444A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55133790A JPS5758444A (en) 1980-09-26 1980-09-26 Clock extracting system in dipulse code composite circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55133790A JPS5758444A (en) 1980-09-26 1980-09-26 Clock extracting system in dipulse code composite circuit

Publications (1)

Publication Number Publication Date
JPS5758444A true JPS5758444A (en) 1982-04-08

Family

ID=15113066

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55133790A Pending JPS5758444A (en) 1980-09-26 1980-09-26 Clock extracting system in dipulse code composite circuit

Country Status (1)

Country Link
JP (1) JPS5758444A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6084042A (en) * 1983-08-29 1985-05-13 エリクソン　ジーイー　モービル　コミュニケーションズ　インコーポレーテッド Clock recovery device
JPS6194429A (en) * 1984-10-15 1986-05-13 Nec Corp Phase synchronizing circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6084042A (en) * 1983-08-29 1985-05-13 エリクソン　ジーイー　モービル　コミュニケーションズ　インコーポレーテッド Clock recovery device
JPS6194429A (en) * 1984-10-15 1986-05-13 Nec Corp Phase synchronizing circuit
JPH0546730B2 (en) * 1984-10-15 1993-07-14 Nippon Electric Co

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