JPS6419821A - Reset synchronization delay circuit - Google Patents
Reset synchronization delay circuitInfo
- Publication number
- JPS6419821A JPS6419821A JP62176255A JP17625587A JPS6419821A JP S6419821 A JPS6419821 A JP S6419821A JP 62176255 A JP62176255 A JP 62176255A JP 17625587 A JP17625587 A JP 17625587A JP S6419821 A JPS6419821 A JP S6419821A
- Authority
- JP
- Japan
- Prior art keywords
- clock signal
- impressed
- outputted
- system clock
- internal clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F02—COMBUSTION ENGINES; HOT-GAS OR COMBUSTION-PRODUCT ENGINE PLANTS
- F02B—INTERNAL-COMBUSTION PISTON ENGINES; COMBUSTION ENGINES IN GENERAL
- F02B75/00—Other engines
- F02B75/02—Engines characterised by their cycles, e.g. six-stroke
- F02B2075/022—Engines characterised by their cycles, e.g. six-stroke having less than six strokes per cycle
- F02B2075/025—Engines characterised by their cycles, e.g. six-stroke having less than six strokes per cycle two
Abstract
PURPOSE:To constantly output an internal clock signal having a delay time more than a constant time by defining a system clock signal outputted through a gate opened by the output of a flip flop impressed in which the system clock signal is impressed to a trigger terminal to be the internal clock signal. CONSTITUTION:A reset signal Vr is impressed to the data terminal D of the flip flop FF in which the system clock signal Vc is impressed to the trigger terminal T, an inverse reset signal Vr' in which the reset signal Vr is inverted is impressed to the set terminal S of said flip flop FF, and the system clock signal Vc outputted through the gate G consisting of a NOR circuit is outputted as the internal clock signal phi. Thereby, the internal clock signal phi having the delay time more than a constant time td (at least 1/2 cycle of system clock signal) constantly to the reset signal Vr is outputted and the pulse of a constant duty is obtained from the beginning.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62176255A JPS6419821A (en) | 1987-07-15 | 1987-07-15 | Reset synchronization delay circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62176255A JPS6419821A (en) | 1987-07-15 | 1987-07-15 | Reset synchronization delay circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6419821A true JPS6419821A (en) | 1989-01-23 |
Family
ID=16010365
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62176255A Pending JPS6419821A (en) | 1987-07-15 | 1987-07-15 | Reset synchronization delay circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6419821A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5116400A (en) * | 1990-09-20 | 1992-05-26 | Corning Incorporated | Apparatus for forming a porous glass preform |
| US5717430A (en) * | 1994-08-18 | 1998-02-10 | Sc&T International, Inc. | Multimedia computer keyboard |
| US5958102A (en) * | 1996-11-27 | 1999-09-28 | Shin-Etsu Chemical Co., Ltd. | Apparatus and method for making an optical fiber preform using a correction pass |
-
1987
- 1987-07-15 JP JP62176255A patent/JPS6419821A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5116400A (en) * | 1990-09-20 | 1992-05-26 | Corning Incorporated | Apparatus for forming a porous glass preform |
| US5717430A (en) * | 1994-08-18 | 1998-02-10 | Sc&T International, Inc. | Multimedia computer keyboard |
| US5958102A (en) * | 1996-11-27 | 1999-09-28 | Shin-Etsu Chemical Co., Ltd. | Apparatus and method for making an optical fiber preform using a correction pass |
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