JPS53139456A - Clock driver circuit - Google Patents
Clock driver circuitInfo
- Publication number
- JPS53139456A JPS53139456A JP5415177A JP5415177A JPS53139456A JP S53139456 A JPS53139456 A JP S53139456A JP 5415177 A JP5415177 A JP 5415177A JP 5415177 A JP5415177 A JP 5415177A JP S53139456 A JPS53139456 A JP S53139456A
- Authority
- JP
- Japan
- Prior art keywords
- driver circuit
- clock driver
- clock signal
- inverse
- coincidence
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Logic Circuits (AREA)
- Shift Register Type Memory (AREA)
- Manipulation Of Pulses (AREA)
Abstract
PURPOSE: To secure a coincidence between the delay time and the rise and fall time when the switching element is driven, by using both the inverse and non-inverse output of the input clock signal as a complementary clock signal each.
COPYRIGHT: (C)1978,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP52054151A JPS5834982B2 (en) | 1977-05-11 | 1977-05-11 | clock driver circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP52054151A JPS5834982B2 (en) | 1977-05-11 | 1977-05-11 | clock driver circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS53139456A true JPS53139456A (en) | 1978-12-05 |
JPS5834982B2 JPS5834982B2 (en) | 1983-07-30 |
Family
ID=12962542
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP52054151A Expired JPS5834982B2 (en) | 1977-05-11 | 1977-05-11 | clock driver circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5834982B2 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55145437A (en) * | 1979-05-01 | 1980-11-13 | Nippon Telegr & Teleph Corp <Ntt> | Controlling system for logic circuit |
JPS60142618A (en) * | 1983-12-28 | 1985-07-27 | Hitachi Ltd | Input buffer circuit |
JPH0334328U (en) * | 1989-08-09 | 1991-04-04 | ||
JPH0684961U (en) * | 1993-05-25 | 1994-12-06 | 義継 豊島 | Full-length |
JP4836024B2 (en) * | 2000-07-10 | 2011-12-14 | エスティー‐エリクソン、ソシエテ、アノニム | A circuit for generating an inverse signal of a digital signal by minimizing a delay difference between the digital signal and the inverse signal. |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS52127051A (en) * | 1976-04-16 | 1977-10-25 | Toshiba Corp | Waveform shaping circuit |
-
1977
- 1977-05-11 JP JP52054151A patent/JPS5834982B2/en not_active Expired
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS52127051A (en) * | 1976-04-16 | 1977-10-25 | Toshiba Corp | Waveform shaping circuit |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55145437A (en) * | 1979-05-01 | 1980-11-13 | Nippon Telegr & Teleph Corp <Ntt> | Controlling system for logic circuit |
JPS60142618A (en) * | 1983-12-28 | 1985-07-27 | Hitachi Ltd | Input buffer circuit |
JPH0334328U (en) * | 1989-08-09 | 1991-04-04 | ||
JPH0684961U (en) * | 1993-05-25 | 1994-12-06 | 義継 豊島 | Full-length |
JP4836024B2 (en) * | 2000-07-10 | 2011-12-14 | エスティー‐エリクソン、ソシエテ、アノニム | A circuit for generating an inverse signal of a digital signal by minimizing a delay difference between the digital signal and the inverse signal. |
Also Published As
Publication number | Publication date |
---|---|
JPS5834982B2 (en) | 1983-07-30 |
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