JPS57162035A - Interruption control system - Google Patents

Interruption control system

Info

Publication number
JPS57162035A
JPS57162035A JP4748181A JP4748181A JPS57162035A JP S57162035 A JPS57162035 A JP S57162035A JP 4748181 A JP4748181 A JP 4748181A JP 4748181 A JP4748181 A JP 4748181A JP S57162035 A JPS57162035 A JP S57162035A
Authority
JP
Japan
Prior art keywords
instruction
register
cpu
processor
iama
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4748181A
Other languages
Japanese (ja)
Inventor
Kiyosumi Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP4748181A priority Critical patent/JPS57162035A/en
Publication of JPS57162035A publication Critical patent/JPS57162035A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0745—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in an input/output transactions management context
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Software Systems (AREA)
  • Complex Calculations (AREA)
  • Advance Control (AREA)

Abstract

PURPOSE:To easily discriminate an instruction which has been generated simultaneously, and to elevate the processing efficiency, by deciding an interruption of a main processor itself by contents of instruction address change information, when a CPU has A simultaneously detected instruction requests from both a main storage device and a subprocessor. CONSTITUTION:An instruction data 1 read out from a main storage device MEM is decoded by an instruction controlling circuit AC of a main processor CPU, and when it is an exclusive instruction of a subprocessor VP, contents of its instruction are sent to the processor VP, and an address of an instruction address register IR is updated whenever the instruction is sent out. On an instruction controlling circuit VAC of this processor VP, an instruction address changing register IAMA is provided, ''1'' is added whenever an instruction from the processor CPU is recived, its operation is executed by an operating circuit VALU, a result of its execution is sent to an operating register AR of the CPU, and the register IAMA is subtracted by ''1'' when the operation has ended. In this way, when the program interruption cause has been generated by the CPU, whether its interruption is executed or not is discriminated by checking a value of the register IAMA. Accordingly, the processing efficiency is elevated.
JP4748181A 1981-03-31 1981-03-31 Interruption control system Pending JPS57162035A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4748181A JPS57162035A (en) 1981-03-31 1981-03-31 Interruption control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4748181A JPS57162035A (en) 1981-03-31 1981-03-31 Interruption control system

Publications (1)

Publication Number Publication Date
JPS57162035A true JPS57162035A (en) 1982-10-05

Family

ID=12776316

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4748181A Pending JPS57162035A (en) 1981-03-31 1981-03-31 Interruption control system

Country Status (1)

Country Link
JP (1) JPS57162035A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0141232A2 (en) * 1983-10-24 1985-05-15 International Business Machines Corporation Vector processing unit
JPS63184168A (en) * 1986-08-20 1988-07-29 Nec Corp Vector computing processor
JPH04106652A (en) * 1990-08-27 1992-04-08 Fujitsu Ltd Exceptional treatment system
JPH04218841A (en) * 1990-03-19 1992-08-10 Fujitsu Ltd Interruption processing system

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0141232A2 (en) * 1983-10-24 1985-05-15 International Business Machines Corporation Vector processing unit
JPS63184168A (en) * 1986-08-20 1988-07-29 Nec Corp Vector computing processor
JPH0528869B2 (en) * 1986-08-20 1993-04-27 Nippon Electric Co
JPH04218841A (en) * 1990-03-19 1992-08-10 Fujitsu Ltd Interruption processing system
JPH04106652A (en) * 1990-08-27 1992-04-08 Fujitsu Ltd Exceptional treatment system

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