JPS5744279A - Cash memory controller - Google Patents

Cash memory controller

Info

Publication number
JPS5744279A
JPS5744279A JP55118627A JP11862780A JPS5744279A JP S5744279 A JPS5744279 A JP S5744279A JP 55118627 A JP55118627 A JP 55118627A JP 11862780 A JP11862780 A JP 11862780A JP S5744279 A JPS5744279 A JP S5744279A
Authority
JP
Japan
Prior art keywords
memory
circuit
operand
address
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55118627A
Other languages
Japanese (ja)
Other versions
JPS6022376B2 (en
Inventor
Hiroyuki Nishimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55118627A priority Critical patent/JPS6022376B2/en
Priority to US06/294,121 priority patent/US4467414A/en
Priority to FR8116082A priority patent/FR2489021B1/en
Publication of JPS5744279A publication Critical patent/JPS5744279A/en
Publication of JPS6022376B2 publication Critical patent/JPS6022376B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0848—Partitioned cache, e.g. separate instruction and operand caches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To increase the hit rate of cash, by processing in preference the data corresponding to an address of the reading request given from a CPU when said address coincides with the contents of an address buffer circuit. CONSTITUTION:Accepting the reading request of a certain instruction from a CPU1, a cash memory control circuit 20 for operand reads the data of a memory address supplied via a line 2 out of an operand cash memory 30 and supplies it to the CPU1. In case no reading request is outputted from the CPU1, the data supplied from a main storage device 4 stored in an operand data buffer circuit 50 is stored in the memory 30. When the memory address of the operand coincides with the data stored in an address buffer circuit 40, an operand coindidence detecting circuit 60 applies a coincidence signal to the circuit 20. Thus the circuit 20 processes in preference the request of storage from the circuit 40. The process to the memory 30 is also executed to an instruction cash memory 31.
JP55118627A 1980-08-22 1980-08-28 Cache memory control device Expired JPS6022376B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP55118627A JPS6022376B2 (en) 1980-08-28 1980-08-28 Cache memory control device
US06/294,121 US4467414A (en) 1980-08-22 1981-08-19 Cashe memory arrangement comprising a cashe buffer in combination with a pair of cache memories
FR8116082A FR2489021B1 (en) 1980-08-22 1981-08-21 ARRANGEMENT OF ANTHEMOIRES COMPRISING A BUFFER ANEMEMORY IN COMBINATION WITH A PAIR OF ANTEMEMORY

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55118627A JPS6022376B2 (en) 1980-08-28 1980-08-28 Cache memory control device

Publications (2)

Publication Number Publication Date
JPS5744279A true JPS5744279A (en) 1982-03-12
JPS6022376B2 JPS6022376B2 (en) 1985-06-01

Family

ID=14741207

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55118627A Expired JPS6022376B2 (en) 1980-08-22 1980-08-28 Cache memory control device

Country Status (1)

Country Link
JP (1) JPS6022376B2 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60123936A (en) * 1983-12-07 1985-07-02 Fujitsu Ltd System for controlling buffer storage
EP0325677A2 (en) * 1988-01-25 1989-08-02 Otto Müller Circuit and method for controlling an instruction buffer in a data-processing system
JPH02239331A (en) * 1989-01-05 1990-09-21 Bull Hn Inf Syst Inc Data processing system and method with heightened operand usability
US6374334B1 (en) 1994-07-04 2002-04-16 Fujitsu Limited Data processing apparatus with a cache controlling device
JP2006242338A (en) * 2005-03-04 2006-09-14 Jms Co Ltd Connector and connection structure
JP2006318471A (en) * 2005-05-09 2006-11-24 Sony Computer Entertainment Europe Ltd Memory caching in data processing

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60123936A (en) * 1983-12-07 1985-07-02 Fujitsu Ltd System for controlling buffer storage
JPH0526212B2 (en) * 1983-12-07 1993-04-15 Fujitsu Ltd
EP0325677A2 (en) * 1988-01-25 1989-08-02 Otto Müller Circuit and method for controlling an instruction buffer in a data-processing system
JPH02239331A (en) * 1989-01-05 1990-09-21 Bull Hn Inf Syst Inc Data processing system and method with heightened operand usability
US6374334B1 (en) 1994-07-04 2002-04-16 Fujitsu Limited Data processing apparatus with a cache controlling device
JP2006242338A (en) * 2005-03-04 2006-09-14 Jms Co Ltd Connector and connection structure
JP2006318471A (en) * 2005-05-09 2006-11-24 Sony Computer Entertainment Europe Ltd Memory caching in data processing
JP4666511B2 (en) * 2005-05-09 2011-04-06 ソニー コンピュータ エンタテインメント ヨーロッパ リミテッド Memory caching in data processing

Also Published As

Publication number Publication date
JPS6022376B2 (en) 1985-06-01

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