JPS57132477A - Decoding system for variable length code - Google Patents
Decoding system for variable length codeInfo
- Publication number
- JPS57132477A JPS57132477A JP56016849A JP1684981A JPS57132477A JP S57132477 A JPS57132477 A JP S57132477A JP 56016849 A JP56016849 A JP 56016849A JP 1684981 A JP1684981 A JP 1684981A JP S57132477 A JPS57132477 A JP S57132477A
- Authority
- JP
- Japan
- Prior art keywords
- code
- inputted
- register
- eol
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
- H04N1/41—Bandwidth or redundancy reduction
- H04N1/411—Bandwidth or redundancy reduction for the transmission or storage or reproduction of two-tone pictures, e.g. black and white pictures
- H04N1/413—Systems or arrangements allowing the picture to be reproduced without loss or modification of picture-information
- H04N1/419—Systems or arrangements allowing the picture to be reproduced without loss or modification of picture-information in which encoding of the length of a succession of picture-elements of the same value along a scanning line is the only encoding step
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
- Facsimile Transmission Control (AREA)
Abstract
PURPOSE:To prevent affection of a code error from extending to the next line, by achieving sure detection of a line synchronizing signal even with the code error. CONSTITUTION:A data DT of a variable length code is inputted to a shift register 1 in synchronizing with a clock CLK. This clock CLK is also inputted to a 0 consecutive counter 5A of an EOL (line synchronizing signal) detection section 5 to count the number of consecutive 0s of data DT inputted to the register 1, and when the count number reaches 11, it is stored with a 11-storing latch circuit 5B. Thereafter, when 1 is inputted to the least significant bit of the register 1, the AND condition of an AND gate circuit 5C is established and this output is recognized as EOL. In this case, the output of the circuit 5C clears the register 1, code length counter 2, FF3, counter 5A, and circuit 5B respectively. Thus, if there is any error in code, the EOL is surely detected.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56016849A JPS57132477A (en) | 1981-02-09 | 1981-02-09 | Decoding system for variable length code |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56016849A JPS57132477A (en) | 1981-02-09 | 1981-02-09 | Decoding system for variable length code |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57132477A true JPS57132477A (en) | 1982-08-16 |
Family
ID=11927655
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56016849A Pending JPS57132477A (en) | 1981-02-09 | 1981-02-09 | Decoding system for variable length code |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57132477A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5579565A (en) * | 1978-12-12 | 1980-06-16 | Fujitsu Ltd | Picture signal decoding system |
-
1981
- 1981-02-09 JP JP56016849A patent/JPS57132477A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5579565A (en) * | 1978-12-12 | 1980-06-16 | Fujitsu Ltd | Picture signal decoding system |
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