JPS5696845A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5696845A
JPS5696845A JP17290879A JP17290879A JPS5696845A JP S5696845 A JPS5696845 A JP S5696845A JP 17290879 A JP17290879 A JP 17290879A JP 17290879 A JP17290879 A JP 17290879A JP S5696845 A JPS5696845 A JP S5696845A
Authority
JP
Japan
Prior art keywords
film
wiring
contact
contact hole
insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17290879A
Other languages
Japanese (ja)
Other versions
JPS6211783B2 (en
Inventor
Toshio Kurahashi
Chuichi Takada
Toshihiko Ono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP17290879A priority Critical patent/JPS5696845A/en
Publication of JPS5696845A publication Critical patent/JPS5696845A/en
Publication of JPS6211783B2 publication Critical patent/JPS6211783B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To enhance the positioning accuracy in the method of manufacturing the semiconductor device by laminating an etching stopper film and a wiring contact metal film on the wiring film of a predetermined layer, forming the metal film equal in shape to the contact hole and surrounding in with an insulating film and thereby eliminating the need of the formation of the contact hole. CONSTITUTION:The first wiring film 12 formed of aluminum or the like, an etching stopper film 13 and a wiring contact metal film 14 are laminated on the substrate 11, and with a photoresist film 15 as a mask the laminated films are patterned using a dry etching to form the edge of the pattern at an acute angle. Then, insulating films 16 such as SiO, SiO2 or the like is surrounded only around the periphery of the lowermost layer 12, the resist film 15 is removed, and a resist film 17 having the same size as the contact hole is formed on the film 14 thus exposed. Thereafter, the film 14 is patterned, is similarly surrounded by the insulating film 18, the second wiring film 19 is covered on the film 14 becoming for contact while the film 19 is extended on the film 18, and a multilayer wiring is formed thereon.
JP17290879A 1979-12-28 1979-12-28 Manufacture of semiconductor device Granted JPS5696845A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17290879A JPS5696845A (en) 1979-12-28 1979-12-28 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17290879A JPS5696845A (en) 1979-12-28 1979-12-28 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5696845A true JPS5696845A (en) 1981-08-05
JPS6211783B2 JPS6211783B2 (en) 1987-03-14

Family

ID=15950564

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17290879A Granted JPS5696845A (en) 1979-12-28 1979-12-28 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5696845A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62238647A (en) * 1986-04-09 1987-10-19 Fujitsu Ltd Forming method for multilayer interconnection
KR100593126B1 (en) * 1999-12-29 2006-06-26 주식회사 하이닉스반도체 Method of forming a metal wiring in a semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4894866A (en) * 1972-03-15 1973-12-06

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4894866A (en) * 1972-03-15 1973-12-06

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62238647A (en) * 1986-04-09 1987-10-19 Fujitsu Ltd Forming method for multilayer interconnection
KR100593126B1 (en) * 1999-12-29 2006-06-26 주식회사 하이닉스반도체 Method of forming a metal wiring in a semiconductor device

Also Published As

Publication number Publication date
JPS6211783B2 (en) 1987-03-14

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