JPS56130925A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS56130925A
JPS56130925A JP3381880A JP3381880A JPS56130925A JP S56130925 A JPS56130925 A JP S56130925A JP 3381880 A JP3381880 A JP 3381880A JP 3381880 A JP3381880 A JP 3381880A JP S56130925 A JPS56130925 A JP S56130925A
Authority
JP
Japan
Prior art keywords
film
etching
pattern
polysilicon
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3381880A
Other languages
Japanese (ja)
Inventor
Kazufumi Ogawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP3381880A priority Critical patent/JPS56130925A/en
Publication of JPS56130925A publication Critical patent/JPS56130925A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers

Abstract

PURPOSE:To smooth the steps of an etching pattern by forming the second film having an etching rate larger than the first film and the first film on a substrate and plasma etching the first and the second films with a resist pattern as a mask. CONSTITUTION:The first film 3 made of polysilicon and the second film 7 made of Mo or the like having a plasma etching rate faster than the film 3 are sequentially laminated on a semiconductor substrate 1 having an insulating film 2, and with a resist pattern 4' as a mask it is plasma etched in CF4 atmosphere to form an etching pattern made of polysilicon. Thus, the step B' of the etching pattern is smoothed with high accuracy, and accordingly the improper disconnection of a metallic wiring layer can be reduced.
JP3381880A 1980-03-17 1980-03-17 Manufacture of semiconductor device Pending JPS56130925A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3381880A JPS56130925A (en) 1980-03-17 1980-03-17 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3381880A JPS56130925A (en) 1980-03-17 1980-03-17 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS56130925A true JPS56130925A (en) 1981-10-14

Family

ID=12397054

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3381880A Pending JPS56130925A (en) 1980-03-17 1980-03-17 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS56130925A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1985000928A1 (en) * 1983-08-08 1985-02-28 Ncr Corporation Process for beveling a metal layer in an integrated circuit
US4645562A (en) * 1985-04-29 1987-02-24 Hughes Aircraft Company Double layer photoresist technique for side-wall profile control in plasma etching processes
JP2011210313A (en) * 2010-03-30 2011-10-20 Dainippon Printing Co Ltd Substrate for suspension, method for manufacturing substrate for suspension, suspension, suspension with element, and hard disk drive

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4924671A (en) * 1972-06-30 1974-03-05
JPS5098786A (en) * 1973-12-27 1975-08-06

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4924671A (en) * 1972-06-30 1974-03-05
JPS5098786A (en) * 1973-12-27 1975-08-06

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1985000928A1 (en) * 1983-08-08 1985-02-28 Ncr Corporation Process for beveling a metal layer in an integrated circuit
US4645562A (en) * 1985-04-29 1987-02-24 Hughes Aircraft Company Double layer photoresist technique for side-wall profile control in plasma etching processes
JP2011210313A (en) * 2010-03-30 2011-10-20 Dainippon Printing Co Ltd Substrate for suspension, method for manufacturing substrate for suspension, suspension, suspension with element, and hard disk drive

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