JPS56164430A - Control system for interrupting priority - Google Patents

Control system for interrupting priority

Info

Publication number
JPS56164430A
JPS56164430A JP6819580A JP6819580A JPS56164430A JP S56164430 A JPS56164430 A JP S56164430A JP 6819580 A JP6819580 A JP 6819580A JP 6819580 A JP6819580 A JP 6819580A JP S56164430 A JPS56164430 A JP S56164430A
Authority
JP
Japan
Prior art keywords
line
address
priority
modules
module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6819580A
Other languages
Japanese (ja)
Inventor
Kinichi Takeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP6819580A priority Critical patent/JPS56164430A/en
Publication of JPS56164430A publication Critical patent/JPS56164430A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To make flexible interruption control at system operation, by changing the priority of each module with the addition of a simple logical circuit, through the comparison between the address inherent to each module connected to bus lines and the address from a control logical section. CONSTITUTION:A plurality of modules 14-16 are connected to a bus line 11, a bus line usage request line 12 is connected to the modules 14-16, and a bus line control logical section 10 is connected to the request line 12. The logical section 10 is connected to the line 11 and a bus line usage request reception line 13 is connected to the modules 14-16. Further, an address signal 8 and a selection signal 5 of the modules 14-16 are outputted from the control section 10, and they are compares with the inherent address of a module inherent address 3 at the comparison circuit 6 of the module 14. When the result is in dissidence a nonselection detecting signal 7 is fed to a gate 4 to renew the information of a counter 2, the priority renewed is fed to a priority display line 9 and the priority is changed.
JP6819580A 1980-05-22 1980-05-22 Control system for interrupting priority Pending JPS56164430A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6819580A JPS56164430A (en) 1980-05-22 1980-05-22 Control system for interrupting priority

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6819580A JPS56164430A (en) 1980-05-22 1980-05-22 Control system for interrupting priority

Publications (1)

Publication Number Publication Date
JPS56164430A true JPS56164430A (en) 1981-12-17

Family

ID=13366754

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6819580A Pending JPS56164430A (en) 1980-05-22 1980-05-22 Control system for interrupting priority

Country Status (1)

Country Link
JP (1) JPS56164430A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01276263A (en) * 1988-04-27 1989-11-06 Agency Of Ind Science & Technol Bus communicating device
JPH0822434A (en) * 1994-07-06 1996-01-23 Nec Corp System bus control circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01276263A (en) * 1988-04-27 1989-11-06 Agency Of Ind Science & Technol Bus communicating device
JPH0528861B2 (en) * 1988-04-27 1993-04-27 Kogyo Gijutsuin
JPH0822434A (en) * 1994-07-06 1996-01-23 Nec Corp System bus control circuit

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