JPS5745657A - Storage device - Google Patents

Storage device

Info

Publication number
JPS5745657A
JPS5745657A JP12076680A JP12076680A JPS5745657A JP S5745657 A JPS5745657 A JP S5745657A JP 12076680 A JP12076680 A JP 12076680A JP 12076680 A JP12076680 A JP 12076680A JP S5745657 A JPS5745657 A JP S5745657A
Authority
JP
Japan
Prior art keywords
storage device
bus
address
data bus
cpu
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12076680A
Other languages
Japanese (ja)
Inventor
Kenzo Nakabashi
Ryoetsu Nakajima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP12076680A priority Critical patent/JPS5745657A/en
Publication of JPS5745657A publication Critical patent/JPS5745657A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE:To make easy the accessing from a CPU, by selecting and switching the address information from the CPU connected to an external storage device and bidirectional data bus and the address signal connected to other device and the bidirectional data bus. CONSTITUTION:The device consists of a storage device 11, register 12, selection circuit 13 selecting the register output with the address signal, and selection circuit 14 which switches the bidirectional bus for a CPU20 and other device 22. Thus, selection circuits 13, 14 are operated with the address bus 31 to the information from the CPU and it is inputted to the storage device 11 via a data bus 30. On the other hand, in case of data transfer from the device 22, the data bus 30 and address bus 31 are detached with the selection circuits 13, 14 and they are directly connected to the storage device 11.
JP12076680A 1980-09-01 1980-09-01 Storage device Pending JPS5745657A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12076680A JPS5745657A (en) 1980-09-01 1980-09-01 Storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12076680A JPS5745657A (en) 1980-09-01 1980-09-01 Storage device

Publications (1)

Publication Number Publication Date
JPS5745657A true JPS5745657A (en) 1982-03-15

Family

ID=14794465

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12076680A Pending JPS5745657A (en) 1980-09-01 1980-09-01 Storage device

Country Status (1)

Country Link
JP (1) JPS5745657A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6383845A (en) * 1986-09-29 1988-04-14 Toshiba Corp Memory card
JPH0535647A (en) * 1991-07-30 1993-02-12 Nec Ic Microcomput Syst Ltd Microcomputer system
US5415390A (en) * 1994-05-23 1995-05-16 Hewlett-Packard Company Double surface registration mechanism for a stack of sheets

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6383845A (en) * 1986-09-29 1988-04-14 Toshiba Corp Memory card
JPH0535647A (en) * 1991-07-30 1993-02-12 Nec Ic Microcomput Syst Ltd Microcomputer system
US5415390A (en) * 1994-05-23 1995-05-16 Hewlett-Packard Company Double surface registration mechanism for a stack of sheets

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