JPS56116158A - Memory block selection circuit - Google Patents

Memory block selection circuit

Info

Publication number
JPS56116158A
JPS56116158A JP1776780A JP1776780A JPS56116158A JP S56116158 A JPS56116158 A JP S56116158A JP 1776780 A JP1776780 A JP 1776780A JP 1776780 A JP1776780 A JP 1776780A JP S56116158 A JPS56116158 A JP S56116158A
Authority
JP
Japan
Prior art keywords
block
address
module
memory
block selection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1776780A
Other languages
Japanese (ja)
Inventor
Akira Komatsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP1776780A priority Critical patent/JPS56116158A/en
Publication of JPS56116158A publication Critical patent/JPS56116158A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G06F12/0653—Configuration or reconfiguration with centralised address assignment

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To prevent all blocks being disable, by detaching a destroyed block only from a memory area. CONSTITUTION:Memory blocks 25-28 are respectively provided with block selection address set switches 29-32 and also comparison circuits 33-36. The comparison circuits 33-36 compare the module selection address 37 indicating module and block among the memory address received at the receiver 11 with the output of the switches 29-32. The address 38 except the module selection address is fed to the memory blocks 25-27 as the information designating the address in each memory block. If the block 1(49) of the module 1 is destroyed, the block selection address switch of the block is detached from the bus as the address not present on the bus, and instead, the block selection address switch of the block 4(56) of the module 2 is operated to operate this block.
JP1776780A 1980-02-18 1980-02-18 Memory block selection circuit Pending JPS56116158A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1776780A JPS56116158A (en) 1980-02-18 1980-02-18 Memory block selection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1776780A JPS56116158A (en) 1980-02-18 1980-02-18 Memory block selection circuit

Publications (1)

Publication Number Publication Date
JPS56116158A true JPS56116158A (en) 1981-09-11

Family

ID=11952856

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1776780A Pending JPS56116158A (en) 1980-02-18 1980-02-18 Memory block selection circuit

Country Status (1)

Country Link
JP (1) JPS56116158A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6255742A (en) * 1985-09-04 1987-03-11 Fujitsu Ltd Bank switching system
JPH01231144A (en) * 1988-03-11 1989-09-14 Nec Corp Memory circuit
JPH05313997A (en) * 1992-05-08 1993-11-26 Nec Corp Read-only memory device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6255742A (en) * 1985-09-04 1987-03-11 Fujitsu Ltd Bank switching system
JPH01231144A (en) * 1988-03-11 1989-09-14 Nec Corp Memory circuit
JPH05313997A (en) * 1992-05-08 1993-11-26 Nec Corp Read-only memory device

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