JPS56108137A - Data communication controller - Google Patents

Data communication controller

Info

Publication number
JPS56108137A
JPS56108137A JP1030080A JP1030080A JPS56108137A JP S56108137 A JPS56108137 A JP S56108137A JP 1030080 A JP1030080 A JP 1030080A JP 1030080 A JP1030080 A JP 1030080A JP S56108137 A JPS56108137 A JP S56108137A
Authority
JP
Japan
Prior art keywords
instruction
acceptance
input
output
decided
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1030080A
Other languages
Japanese (ja)
Inventor
Takuma Fukuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP1030080A priority Critical patent/JPS56108137A/en
Publication of JPS56108137A publication Critical patent/JPS56108137A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To accept and store the input/output instructions given from a processor up to two units regardless of the idle mode or the data transmission mode, thus securing an acceptance for one input/output instruction even though the other instruction is being executed. CONSTITUTION:The input/output instruction sent from the central processor is transferred and stored into the instruction acceptance/storage part register 12 or 13 if it is decided acceptable by the display input of the state of acceptance of the instruction acceptance/display parts 14 and 15 which is received at the deciding part 10. Then the corresponding display 14 or 15 is set. If the setting of both displays 14 and 15 is decided at the part 10, the busy signal is sent back to the central processor. The instruction execution control part 16 extracts alternately the instructions given from the registers 12 and 13 by the displays 14 and 15, and then transfers the extracted instructions to the instruction execution part by the FREE signal indicating the idle state of the instruction execution part 17. Thus an execution is indicated for the instruction.
JP1030080A 1980-01-31 1980-01-31 Data communication controller Pending JPS56108137A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1030080A JPS56108137A (en) 1980-01-31 1980-01-31 Data communication controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1030080A JPS56108137A (en) 1980-01-31 1980-01-31 Data communication controller

Publications (1)

Publication Number Publication Date
JPS56108137A true JPS56108137A (en) 1981-08-27

Family

ID=11746404

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1030080A Pending JPS56108137A (en) 1980-01-31 1980-01-31 Data communication controller

Country Status (1)

Country Link
JP (1) JPS56108137A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05242055A (en) * 1991-11-19 1993-09-21 Internatl Business Mach Corp <Ibm> Distributed memory-type digital calculating system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05242055A (en) * 1991-11-19 1993-09-21 Internatl Business Mach Corp <Ibm> Distributed memory-type digital calculating system

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