JPS57101928A - Interruption controlling system - Google Patents

Interruption controlling system

Info

Publication number
JPS57101928A
JPS57101928A JP55178409A JP17840980A JPS57101928A JP S57101928 A JPS57101928 A JP S57101928A JP 55178409 A JP55178409 A JP 55178409A JP 17840980 A JP17840980 A JP 17840980A JP S57101928 A JPS57101928 A JP S57101928A
Authority
JP
Japan
Prior art keywords
interruption
cpu
received
sets
reads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55178409A
Other languages
Japanese (ja)
Inventor
Nobuyuki Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP55178409A priority Critical patent/JPS57101928A/en
Publication of JPS57101928A publication Critical patent/JPS57101928A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To decrease the hardware logic and to simplify the control, by saving the contents of an interruption FF until preparations for receiving the next interruption are completed after a CPU has received said contents, and taking synchronization of the CPU and a channel device by multiple interruption. CONSTITUTION:A bus interface device 11 of a channel device 1 is connected between a system bus 2 and an internal bus of a processor 12, and it is controlled to send and receive data to and from an external device. For instance, when a interruption request is given to the device 1 from an input/output device, the device sets a logical channel number and status to an interruption information area being present in a main storage device or an RAM14, and sets an interruption FF21. On the other hand, when the interruption is received, a CPU sets an interruption mask, reads a channel number of said interruption, and reads the interruption information. In this way, the CPU sends out a signal for resetting the FF21, to the device 1 which has received the interruption, through an interruption controlling signal INT.
JP55178409A 1980-12-17 1980-12-17 Interruption controlling system Pending JPS57101928A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55178409A JPS57101928A (en) 1980-12-17 1980-12-17 Interruption controlling system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55178409A JPS57101928A (en) 1980-12-17 1980-12-17 Interruption controlling system

Publications (1)

Publication Number Publication Date
JPS57101928A true JPS57101928A (en) 1982-06-24

Family

ID=16047979

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55178409A Pending JPS57101928A (en) 1980-12-17 1980-12-17 Interruption controlling system

Country Status (1)

Country Link
JP (1) JPS57101928A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60205767A (en) * 1984-03-30 1985-10-17 Fujitsu Ltd Data processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60205767A (en) * 1984-03-30 1985-10-17 Fujitsu Ltd Data processor

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