JPS5592026A - Pulse period monitor circuit - Google Patents

Pulse period monitor circuit

Info

Publication number
JPS5592026A
JPS5592026A JP16240578A JP16240578A JPS5592026A JP S5592026 A JPS5592026 A JP S5592026A JP 16240578 A JP16240578 A JP 16240578A JP 16240578 A JP16240578 A JP 16240578A JP S5592026 A JPS5592026 A JP S5592026A
Authority
JP
Japan
Prior art keywords
period
pulse period
input signal
monostable
monitor circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16240578A
Other languages
Japanese (ja)
Inventor
Kunihiko Kawanishi
Koji Mizushima
Kouchi Ro
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16240578A priority Critical patent/JPS5592026A/en
Publication of JPS5592026A publication Critical patent/JPS5592026A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make it possible to monitor surely the period of pulses by setting previously trigger states of the first and the second retriggerrable monostable multivibrators.
CONSTITUTION: Input signal A is applied to input terminal A1 of the first monostable multivibrator 10, and the output Q1 is sent to input terminal A2 of the second monostable multivibrator 20 and is outputted from Q2. These monostable multivibrators 10 and 20 are retriggerrable, and monostable multivibrators 10 and 20 have trigger states set by a period time shorter than the normal pulse period of the input signal and a period time longer than the normal pulse period of the input signal respectively. Consequently, the period can be monitored surely without clear clocks.
COPYRIGHT: (C)1980,JPO&Japio
JP16240578A 1978-12-29 1978-12-29 Pulse period monitor circuit Pending JPS5592026A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16240578A JPS5592026A (en) 1978-12-29 1978-12-29 Pulse period monitor circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16240578A JPS5592026A (en) 1978-12-29 1978-12-29 Pulse period monitor circuit

Publications (1)

Publication Number Publication Date
JPS5592026A true JPS5592026A (en) 1980-07-12

Family

ID=15753971

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16240578A Pending JPS5592026A (en) 1978-12-29 1978-12-29 Pulse period monitor circuit

Country Status (1)

Country Link
JP (1) JPS5592026A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63193607A (en) * 1987-02-05 1988-08-10 Victor Co Of Japan Ltd Detecting circuit for duty cycle of signal

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63193607A (en) * 1987-02-05 1988-08-10 Victor Co Of Japan Ltd Detecting circuit for duty cycle of signal

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