JPS55644A - Television picture receiver - Google Patents

Television picture receiver

Info

Publication number
JPS55644A
JPS55644A JP7339678A JP7339678A JPS55644A JP S55644 A JPS55644 A JP S55644A JP 7339678 A JP7339678 A JP 7339678A JP 7339678 A JP7339678 A JP 7339678A JP S55644 A JPS55644 A JP S55644A
Authority
JP
Japan
Prior art keywords
circuit
video signal
time axis
video
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7339678A
Other languages
Japanese (ja)
Inventor
Yoshio Yasumoto
Namio Yamaguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP7339678A priority Critical patent/JPS55644A/en
Publication of JPS55644A publication Critical patent/JPS55644A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To increase the longitudinal smoothness of the luminance screen as well as S/N by incorporating the video signal time axis process circuit and then glowing the horizontal flyback line with the signal obtained by giving the time axis inversion and time axis compression to the luminance signal among the video signals. CONSTITUTION:The video signal passed through antenna 1, tuner 2 and VIF detection circuit 3 is supplied to cathode-ray tube 9 from video output circuit 8 via video signal process circuit 4, chroma signal process circuit 5, color demodulator circuit 6 and matrix circuit 7 each. At the same time, the video signal is deflected 13 by the signals sent from synchronous isolation circuit 10 plus horizontal and vertical deflecting circuits 11 and 12. Then video signal time axis process circuit 14 is provided at the front or rear step of circuit 4. The pulse is supplied from horizontal deflecting circuit 11 for the time switching control. On the other hand, video output circuit 8 is controlled so that the horizontal flyback line may not erased.
JP7339678A 1978-06-16 1978-06-16 Television picture receiver Pending JPS55644A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7339678A JPS55644A (en) 1978-06-16 1978-06-16 Television picture receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7339678A JPS55644A (en) 1978-06-16 1978-06-16 Television picture receiver

Publications (1)

Publication Number Publication Date
JPS55644A true JPS55644A (en) 1980-01-07

Family

ID=13516988

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7339678A Pending JPS55644A (en) 1978-06-16 1978-06-16 Television picture receiver

Country Status (1)

Country Link
JP (1) JPS55644A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57133170U (en) * 1981-02-14 1982-08-19

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57133170U (en) * 1981-02-14 1982-08-19

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