JPS5481707A - Synthesizer receiver - Google Patents

Synthesizer receiver

Info

Publication number
JPS5481707A
JPS5481707A JP14964677A JP14964677A JPS5481707A JP S5481707 A JPS5481707 A JP S5481707A JP 14964677 A JP14964677 A JP 14964677A JP 14964677 A JP14964677 A JP 14964677A JP S5481707 A JPS5481707 A JP S5481707A
Authority
JP
Japan
Prior art keywords
frequency
vco
pll
controlling
demultiplier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14964677A
Other languages
Japanese (ja)
Inventor
Teruo Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP14964677A priority Critical patent/JPS5481707A/en
Publication of JPS5481707A publication Critical patent/JPS5481707A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits
    • H04B1/26—Circuits for superheterodyne receivers

Abstract

PURPOSE:To increase the transient response and the frequency stability, by controlling VCO according to the output frequency of the frequency demultiplier and VCO of PLL. CONSTITUTION:The oscillation frequency of VCO 5 of the PLL frequency synthesizer 4 and the frequency corresponding to the frequency dividing ratio of the programmable frequency demultiplier 6 are compared with the circuit 21, and the positive or negative output pulse according to the magnitude of the both frequencies is superimposed on the DC control signal from LPF 9 and is fed to VCO 3, controlling the oscillation frequency. As a result, the time until the oscillation frequency is completely locked can be reduced.
JP14964677A 1977-12-13 1977-12-13 Synthesizer receiver Pending JPS5481707A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14964677A JPS5481707A (en) 1977-12-13 1977-12-13 Synthesizer receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14964677A JPS5481707A (en) 1977-12-13 1977-12-13 Synthesizer receiver

Publications (1)

Publication Number Publication Date
JPS5481707A true JPS5481707A (en) 1979-06-29

Family

ID=15479765

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14964677A Pending JPS5481707A (en) 1977-12-13 1977-12-13 Synthesizer receiver

Country Status (1)

Country Link
JP (1) JPS5481707A (en)

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