JPS56137736A - Phase-synchronizing circuit - Google Patents

Phase-synchronizing circuit

Info

Publication number
JPS56137736A
JPS56137736A JP4014880A JP4014880A JPS56137736A JP S56137736 A JPS56137736 A JP S56137736A JP 4014880 A JP4014880 A JP 4014880A JP 4014880 A JP4014880 A JP 4014880A JP S56137736 A JPS56137736 A JP S56137736A
Authority
JP
Japan
Prior art keywords
frequency
output
phase
synchronizing circuit
lower limit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4014880A
Other languages
Japanese (ja)
Inventor
Yoshimitsu Ishiro
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Anritsu Corp
Original Assignee
Anritsu Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Anritsu Corp filed Critical Anritsu Corp
Priority to JP4014880A priority Critical patent/JPS56137736A/en
Publication of JPS56137736A publication Critical patent/JPS56137736A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/06—Phase locked loops with a controlled oscillator having at least two frequency control terminals

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE:To realize a stable phase-synchronizing circuit of simple circuit constitution with excellent C/N, by integrating the output of a frequency phase comparator, by comparing the integral value with upper and lower limit values of frequencies which can be phase-synchronized, and by correcting a rough tuning frequency by extent equivalent to the difference. CONSTITUTION:The output of frequency controlling oscillator 1, frequency-divided by frequency converter 5, is inputted to frequency phase comparator 3 and then compared with the output of reference signal generator 4 to input the voltage signal that corresponds to the phase difference between both the output signals to loop filter 2, which extract its DC component to control the oscillation frequency of frequency controlling oscillator 1. The output signal of frequency phase comparator 3, on the other hand, is integrated by integrator 7, whose output is applied to frequency synchronizing circuit 8. Then, it is compared with preset upper and lower limit comparison voltages and if it is greater than the upper limit value or less than the lower limit value, a signal for correcting a rough tuning frequency is supplied from frequency synchronizing circuit 8 to the rough tuning control terminal of frequency controlling oscillator 1.
JP4014880A 1980-03-31 1980-03-31 Phase-synchronizing circuit Pending JPS56137736A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4014880A JPS56137736A (en) 1980-03-31 1980-03-31 Phase-synchronizing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4014880A JPS56137736A (en) 1980-03-31 1980-03-31 Phase-synchronizing circuit

Publications (1)

Publication Number Publication Date
JPS56137736A true JPS56137736A (en) 1981-10-27

Family

ID=12572678

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4014880A Pending JPS56137736A (en) 1980-03-31 1980-03-31 Phase-synchronizing circuit

Country Status (1)

Country Link
JP (1) JPS56137736A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61144125A (en) * 1984-12-14 1986-07-01 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Phase lock loop circuit apparatus
US6320574B1 (en) 1997-02-24 2001-11-20 Genesis Microchip, Corp. Circuit and method for generating pixel data elements from analog image data and associated synchronization signals

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61144125A (en) * 1984-12-14 1986-07-01 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Phase lock loop circuit apparatus
US6320574B1 (en) 1997-02-24 2001-11-20 Genesis Microchip, Corp. Circuit and method for generating pixel data elements from analog image data and associated synchronization signals
USRE40859E1 (en) 1997-02-24 2009-07-21 Genesis Microchip (Delaware) Inc. Method and system for displaying an analog image by a digital display device
USRE41192E1 (en) * 1997-02-24 2010-04-06 Genesis Microchip Inc. Method and system for displaying an analog image by a digital display device
USRE42615E1 (en) 1997-02-24 2011-08-16 Genesis Microchip (Delaware) Inc. Method and system for displaying an analog image by a digital display device
USRE43573E1 (en) 1997-02-24 2012-08-14 Genesis Microchip (Delaware) Inc. Method and system for displaying an analog image by a digital display device

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