JPH11312138A - Interrupt control system and its control method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize an interrupt control system, capable of reducing the load of a CPU, shortening interrupt detection time and reducing the useless use of a system bus, etc. SOLUTION: Each of plural devices 7 to 9 transfers the information of an interruption factor register to a main memory 5 monitored by a CPU 1 by using direct memory access(DMA) at the same timing as the timing of interruption, so that the interrupt register reading processing of all the devices 7 to 9 which is executed by the CPU 1 can be reduced by one DMA transfer. Thereby the CPU 1 can quickly recognize the interrupt factors of the devices 7 to 9, the processing time can be shortened, the wasteful use of the system bus can be removed, and the load of the CPU and the system bus can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an interrupt control system and a control method thereof, and more particularly to an interrupt control system for various devices connected to a personal computer, an engineering workstation, an office computer, a general-purpose computer, and the like.

[0002]

2. Description of the Related Art As an example of an interrupt control method in such an information processing system, a CPU (Central Processing Unit) monitors interrupts from a plurality of devices. The CPU reads the interrupt factor register for each device from the CPU to identify which device caused the interrupt and to identify (determine) the device that raised the interrupt. Further, the interrupt factor is also recognized, and thereafter, the interrupt factor is reset (the interrupt factor register is reset), and the next CPU processing operation for the interrupt is performed.

FIG. 6 shows a general schematic block diagram of the above-described information processing system, and includes a CPU 1, a cache memory 2, a cache controller 3, a memory controller 4, a main memory (main storage device) 5, And a system bus 10. The system bus 10 includes an address bus 11, a data bus 12, and a control bus 13.

Further, various devices 7 to 9 are provided, and these devices are connected to the system bus 10 via the local bus 14 and the bus bridge 6. The local bus 14 includes an address bus 15 and a data bus 16
And a control bus 17. In addition, 18
Is a bus for interruption from each of the devices 7 to 9, and CP
Connected to U1.

FIG. 7 is a flowchart showing an outline of an interrupt control operation in the information processing system shown in FIG. When a certain device generates an interrupt, the CPU 1 detects this interrupt (step S21). Then CPU
1 reads the contents of the interrupt factor register for all devices 7 to 9 (step S22). When recognizing the contents of all these interrupt factor registers, the CPU 1 limits the device that generated the interrupt (step S2).
3). The interrupt factor of the device that generated the interrupt is reset (step S24). The CPU 1 confirms that the interrupt factor of the device has been reset, and starts the next process for the interrupt requested by the device (step S2).
5, 26).

In this manner, a series of processes for an interrupt is performed. However, it takes a long time for an operation from the occurrence of an interrupt from the devices 7 to 9 to the CPU 1 executing the next process for the interrupt. Become. It is required to reduce a series of processing time related to the interrupt. For example, as disclosed in Japanese Patent Application Laid-Open No. Sho 59-20057, it has been proposed to use DMA (Direct Memory Access). .

In JP-A-59-20057, a slave station writes data for diagnosis to a main memory using a DMA via a master station, and monitors whether or not the written data is correct to diagnose an abnormality. Detects and, if an error is detected, the CPU
The abnormality is diagnosed by giving an interrupt to the system. By storing the data for diagnosis in the main memory, function diagnosis between the slave station and the master station becomes possible, and a highly reliable centralized monitoring and control system becomes possible. However, in this technique, DM
A can be used to determine whether an error has occurred. However, if an error is detected, it is necessary to interrupt the CPU.

In Japanese Patent Application Laid-Open No. 9-204311, an interrupt factor of a device is temporarily stored in a buffer, and when the interrupt factor is accumulated to a certain extent, an interrupt is issued to a CPU.
This technique transfers accumulated interrupt factors to the CPU by DMA, and is an effective technique when there are many interrupt factors and the urgency of interrupt is low.

[0009]

In the prior art shown in FIGS. 6 and 7 described above, an interrupt from the device occurs and the CP is generated.
There is a problem that it takes time for the operation until the U executes the processing for the interrupt. This is because the CPU needs to execute the series of processes shown in FIG. 7 by an interrupt, that is, when a device gives an interrupt, the CPU immediately checks which connected device gives the interrupt. Since it is not possible, read the interrupt factor register for all devices for confirmation,
This is because it is necessary to limit which device. Also, since it takes time for the CPU interrupt processing,
There is also a problem that the load on the CPU increases accordingly.

[0010] Further, since the system bus is used during a series of interrupt processing, there is a problem that access to other devices may be affected. This means that when the CPU detects an interrupt process from the device,
The CPU reads the interrupt factor register for each device in order to limit the interrupt from which device out of a plurality of devices, and to recognize the type of interrupt. This is because the processing of the device is waited.

In Japanese Patent Application Laid-Open No. 59-20057, as described above, interrupt factors of a device are temporarily stored in a buffer, an interrupt is issued to a CPU when the interrupt factors are accumulated to some extent, and the accumulated interrupt factors are determined by a CPU using a DMA. This is an effective technique when there are many interrupt factors and the urgency of interrupt is low, and is unsuitable for interrupt processing in a device with high urgency. Also, an interrupt to the CPU is necessary as in the example of FIG.
However, there is a problem that it does not lead to a reduction in the load on the vehicle.

An object of the present invention is to reduce the load on a CPU,
An object of the present invention is to provide an interrupt control system and a control method capable of shortening an interrupt detection time and reducing useless use of a system bus.

[0013]

According to the present invention, a CPU is provided.
An interrupt control system in an information processing apparatus, comprising: a main storage device; and a plurality of devices that issue an interrupt request to the CPU and allow DMA (direct memory access) to the main storage device. The present invention provides an interrupt control system characterized in that the interrupt factor information is written to the main storage device by DMA every time the interrupt factor occurs.

The main storage device has an address pre-assigned to each of the devices, and each of the devices performs the DMA write to the address assigned to itself. The invention is characterized in that the CPU monitors interrupt factor information written in the main storage device.

Further, the CPU resets the interrupt factor for a device that has generated the interrupt factor information obtained by monitoring the main storage device, and the CPU resets the interrupt factor. After the resetting, the processing of the interrupt factor is executed.

According to the present invention, there is provided an interrupt control method in which a plurality of devices generate an interrupt request to a CPU, wherein each of the devices responds to the occurrence of the interrupt cause by setting a predetermined value in the main storage device. An interrupt control method characterized by including a step of writing the interrupt factor information by DMA to the assigned address.

The method may further include the step of the CPU monitoring the interrupt factor information written in the main storage device, and the CPU stores the interrupt factor information obtained by monitoring the main storage device. The method further includes the step of resetting the interrupt factor for the generated device, and the method further includes the step of executing the process of the interrupt factor after the CPU resets the interrupt factor.

The operation of the present invention will be described. Each of the plurality of devices transfers the information of the interrupt factor register to the main storage device monitored by the CPU by using the DMA at the same timing as when the interrupt is issued, so that the C
The read processing of the interrupt factor register for all devices performed by the PU is reduced by one DMA transfer. Therefore, the CPU can quickly recognize the interrupt factor of the device, shorten the processing time, and eliminate unnecessary use of the system bus, and further reduce the load on the CPU and the system bus. Will lead to

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a schematic block diagram showing an embodiment of the present invention, and the same parts as those in FIG. 6 are denoted by the same reference numerals. In the configuration of FIG. 1, the interrupt bus 18 in FIG. 6 is omitted, and the devices 7 to 9 write the contents of the interrupt factor register (interrupt factor information) to the main memory 5 by the DMA function of each device. It is like.

In this case, it is assumed that the addresses of the main memory 5 where the devices 7 to 9 should store the interrupt cause information by DMA are assigned in advance by the system. For example, when an interrupt factor occurs in the device 7, the device 7 writes the contents of the interrupt factor register to a predetermined address of the main memory 5 using DMA. The CPU 1 monitors these addresses of the main memory 5 and recognizes the contents of the interrupt factor register of the main memory 5 rewritten by the device 7 by this monitoring. Is performed.

FIG. 2 is a flowchart showing the outline of the operation of the block shown in FIG. The CPU 1 reads the specific address of the main memory 5 where the interrupt cause is stored, and checks the contents of the cause of each of the devices 7 to 9 (step S).
1). In the second and subsequent reads from the CPU 1 to the main memory 5, the data from the first read is stored in the cache memory 2.
Until data stored in the cache memory 2 is rewritten, the interrupt factors of the devices 7 to 9 can be confirmed without using the system bus 10 and the local bus 14.

The CPU 1 confirms the interrupt factor and resets the interrupt factor register for each of the devices 7 to 9 (steps S2 and S3). If there is a processing request to the devices 7 to 9 (step S4),
9 is issued (step S5). The devices 7 to 9 notify the CPU 1 of the end of the processing by writing the cause of the interrupt to the main memory 5 by DMA instead of the interrupt.

FIG. 3 is a block diagram of an embodiment of the present invention, and the same parts as those in FIG. 1 are denoted by the same reference numerals. In the present embodiment, the various devices 7 to 9 include an HDD (hard disk drive) device, a graphics device,
This figure shows a case where FDD (floppy disk drive) devices are used, respectively, and other configurations are the same as those of FIG.

First, it is necessary to determine an address of the main memory 5 for storing interrupt factor information by DMA in this system. Therefore, the address for storing the interrupt factor information by the HDD device 7 is “0100”,
It is assumed that an address for storing interrupt factor information by the graphics device 8 is “0101” and an address for storing interrupt factor information by the FDD device 9 is “0102”. Therefore, the CPU 1 sets the address “0” of the main memory 5
The data of "100" to "0102" will be monitored.

Here, when an interrupt factor occurs in the FDD device 9, the FDD device 9 transfers the contents of the interrupt factor register to the main memory 5 using DMA.
The CPU 1 recognizes the contents of the interrupt cause register of the main memory 5 rewritten by the FDD device 9, and then performs reset processing of the interrupt cause register for the FDD device 9. The CPU 1 reads the main memory 5 at first, but is cached in the cache memory 2 for the second and subsequent times. Therefore, the CPU 1 monitors the cache memory 2 until the information of the interrupt factor in the main memory 5 is rewritten.

Next, for example, the graphics device 8
Will be described in which the process of reading image data from the main memory 5 by DMA and displaying an image on a display is repeated.

In the case of the conventional example shown in FIGS.
In A, an interrupt is issued each time the transfer of image data is completed. When the graphics device gives an interrupt, the CPU reads the contents of each interrupt cause register for all devices 7 to 9 and checks the contents of the interrupt cause register of the graphics device to determine that the DMA processing has been completed. After confirming, the process of resetting the interrupt cause register for the graphics device is performed, and then the process of issuing the next instruction to the graphics device is repeated many times.

In this embodiment, every time the transfer of the image data by the DMA is completed, the DM of the image data is stored in the content storage address “0101” of the interrupt factor register of the main memory 5.
The CPU 1 can recognize the end of the transfer of the image data of the graphics device 8 only by transferring the content of the interrupt factor indicating that the A transfer has been completed. Then the CPU
1 resets the contents of the interrupt factor register of the graphics device 8 and issues the next instruction to the graphics device 8.

As described above, when the graphics device 8
CP that the transfer of image data is completed using MA
By notifying U1, the CPU 1 can quickly recognize the cause of the interrupt, and further, it is possible to reduce the number of cycles for reading the interrupt cause register for all devices in order to limit the devices that have caused the interrupt. Therefore, C
The load on the PU 1 can be reduced, and the system bus 10 and the local bus 14 can be effectively used.

FIG. 4 is a diagram showing an example of the contents of an interrupt cause register of each of the devices 7 to 9. FIG. 4A shows that the register has a 32-bit configuration of 0 to 31. FIG. 3B shows the specific contents of these 32 bits, 0 to 31, which are examples of the contents of the interrupt factor register in the case of the graphic device 8 in FIG.

The 10th bit indicates an "interruption factor of image data transfer end", where "1" indicates a factor and "0" indicates no factor. The 22nd bit is “FIFO
(Interruption factor indicating that it is no longer necessary to care about the remaining amount of the (temporary storage buffer for image data)), "1" indicates a factor, and "0" indicates no factor.

The 23rd bit indicates the "interruption factor indicating that the remaining amount of the FIFO has decreased". "1" indicates a factor, and "0" indicates no factor. And
The 24th to 28th bits indicate a “remaining amount counter value indicating the remaining amount of the FIFO”. The other bits are reserved.
And “empty (unused)”.

FIG. 5 is an operation flowchart in the case where the graphic device 8 having the interrupt factor register shown in FIG. 4 repeats the process of reading image data from the main memory 5 by DMA and displaying an image on a display. The following describes a case where image data is continuously written to the FIFO in the graphic device 8. At this time, if the transfer speed at which the image data is supplied is higher than the transfer speed at which the image is drawn on the display, the F
Data will accumulate in the IFO.

Therefore, the FI
The remaining amount of the FO is monitored (step S11), and when it is recognized that the remaining amount has decreased (step S1).
2) In the graphic device, the 23 bits of the interrupt factor register are set to "1", and a DMA write is executed at a predetermined address "0101" of the main memory 5 (steps S12 and S13).

The CPU 1 monitors the address "0101", recognizes that the remaining amount of the FIFO has decreased, and thereafter clears the interrupt factor of the interrupt factor register to the graphic device 8 to thereby check the remaining amount of the FIFO. The image data is transferred so as not to overflow the FIFO by checking the quantity counter value (bits 24 to 28) (step S14). When all the image data is transferred to the graphic device 8, the data in the FIFO is sequentially reduced. The graphic device 8 sets 22 bits to "1" and performs DMA write to the address "0101" of the main memory 5 (step S15).

The CPU 1 monitors the address "0101" and recognizes that it is no longer necessary to care about the remaining amount of the FIFO, and clears the interrupt factor to the graphic device 8 so as to clear the remaining amount of the FIFO. Look at the quantity counter value and
Data transfer can be performed without overflowing the IFO (step S16).

When all the image data in the FIFO is drawn on the display (step S17), the graphic device 8 sets 10 bits to "1" and performs DMA write to the address "0101" of the main memory 5 (step S1).
8). The CPU 1 monitors this address "0101", recognizes that the rendering of the image data has been completed, clears the interrupt factor for the graphic device 8, and starts the next operation (step 19).

In the above embodiment, the system specifies the address of the main memory at which the device writes the contents of the interrupt factor register by DMA, but the CPU issues a data transfer instruction by DMA to each device. In this case, it is also possible to notify the CPU of the interrupt factor indicating that the device has started the DMA and has received the data by writing "all0" to the start address of the DMA set by the CPU. In this case, it is possible to solve the problem that it is necessary to allocate an address for writing the content of the interrupt cause to the main memory by the amount of issuing the DMA data transfer instruction to the device.

Referring to the example of FIG. 3, it is assumed that some image data is prepared in the main memory 5, data is sequentially transferred to the graphic device 8, and the display is repeatedly displayed. The first data is interrupt control data so that the start address of the image data DMA can recognize that the DMA of the graphic device 8 has been completed without providing an interrupt factor storage address in the main memory 5. When the DMA transfer of the image data is completed, the graphic device 8 writes “all0” to the start address and completes the process. By monitoring the successively issued start addresses, the CPU 1 can know whether or not the transfer of the image data has been completed.

[0041]

According to the present invention, there is an effect that a series of processing time required for interrupt processing can be greatly reduced. The reason is that the device writes the information of the interrupt factor to a specific address of the main memory by DMA, and
This is because the PU only needs to poll the main memory in which the interrupt factor information is stored. Also, CP
After accessing the main memory once, U can access the cache memory as long as the contents of the memory are not rewritten, so that the speed can be increased.

Further, according to the present invention, there is an effect that the load on the CPU can be reduced and the efficiency of the system bus can be increased. The reason is that the CPU does not need to read the interrupt factor register for all devices,
Is used, the CPU can recognize the cause of the interrupt from the device by the interrupt processing promptly and without almost occupying the bus, and perform the next processing.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an outline of the present invention.

FIG. 2 is a flowchart for explaining the operation of the block in FIG. 1;

FIG. 3 is a block diagram of an embodiment of the present invention.

FIG. 4 is a diagram showing the contents of an interrupt factor register of the device.

FIG. 5 is a flowchart showing details of the operation of one embodiment of the present invention.

FIG. 6 is a schematic block diagram for explaining a conventional interrupt control method.

FIG. 7 is a flowchart for explaining the operation of the block in FIG. 6;

[Description of Signs] 1 CPU 2 Cache memory 3 Cache controller 4 Memory controller 5 Main memory 6 Bus bridge 7 to 9 Device 10 System bus 14 Local bus

Claims (9)

[Claims] 1. An interrupt control system in an information processing apparatus having a CPU, a main storage device, and a plurality of devices that issue an interrupt request to the CPU and that can perform DMA (direct memory access) to the main storage device. An interrupt control system, wherein each of the devices writes the interrupt factor information to the main storage device by DMA each time the interrupt factor occurs. 2. The main storage device has a pre-assigned address for each of the devices, and each of the devices stores the DM in an address assigned to itself.
2. The interrupt control system according to claim 1, wherein an A write is performed. 3. The interrupt control system according to claim 1, wherein said CPU monitors interrupt factor information written in said main storage device. 4. The interrupt control according to claim 3, wherein the CPU resets the interrupt factor for a device that has generated the interrupt factor information obtained by monitoring the main storage device. system. 5. The interrupt control system according to claim 4, wherein said CPU executes processing of the interrupt factor after resetting the interrupt factor. 6. An interrupt control method in which a plurality of devices generate an interrupt request to a CPU, wherein each of the devices responds to the occurrence of the interrupt factor by setting a predetermined address of the main storage device. An interrupt control method comprising writing the interrupt factor information by DMA on the other hand. 7. The interrupt control method according to claim 6, further comprising the step of said CPU monitoring interrupt factor information written in said main storage device. 8. The interrupt according to claim 7, further comprising the step of the CPU resetting the interrupt factor for a device that has generated the interrupt factor information obtained by monitoring the main storage device. Control method. 9. The interrupt control method according to claim 8, further comprising the step of executing processing of the interrupt factor after the CPU resets the interrupt factor.