JP3266184B2 - I / O control method and device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an input / output control method connected to an input / output bus of an information processing apparatus and an apparatus therefor.

[0002]

2. Description of the Related Art Conventionally, in a bus cycle of an input / output control device connected to an input / output bus of an information processing device, a monitoring timer is used to prevent a specific bus master from occupying the bus for a long time. When the time exceeds a preset time, the bus is opened. For example, Japanese Patent Laying-Open No. 1-448154 discloses a time-out monitoring circuit that monitors the time that a bus is occupied and, when the occupation time exceeds a preset time, issues a signal that causes the bus master to release the bus. A bus arbitration circuit is described.

FIG. 5 is a diagram showing a configuration of an information processing system to which a conventional input / output control device is applied. According to the figure, an information processing system to which a conventional input / output control device is applied includes a system bus 560 and an input / output bus 570. The system bus 560 includes a central processing unit 5
10 and the main storage device 520 are connected. I / O bus 5
A plurality of input / output control devices 550 are connected to 70.
A bus connection device 530 is connected between the system bus 560 and the input / output bus 570. I / O bus 5
A bus control device 540 for monitoring this is connected to 70.

[0004] The central processing unit 510 is a device for performing various operations and the like, and has a role of issuing input / output instructions. The main storage device 520 stores data to be executed and instructions and input / output instructions. The main storage device 520 sends data onto the system bus 560 in response to a memory read request from the central processing unit 510 or the bus connection device 530, and stores the data on the system bus 560 at the specified address in a memory write request. I do. The bus connection device 530 connects between the system bus 560 and the input / output bus 570, and performs protocol conversion and the like.

The input / output control device 550 connects an input / output device (not shown). Further, the input / output control device 550 includes a bus master timer register 554 for storing therein a set value previously set as a bus occupancy time, a bus master timer counter 553 for counting the time of operating as a bus master, and a bus master timer counter 553. A timeout detection circuit 552 for detecting a match between the timer and the bus mass timer register 554 and notifying a timeout, and an input / output interface circuit 551 for terminating data transfer in response to the notification from the timeout detection circuit 552 are included.

In the above-mentioned prior art, when the occupation time of the bus reaches a preset time, the input / output control device starts the operation of terminating the data transfer, and performs the remaining data transfer when the bus is next occupied. .

[0007] For example, see Japanese Patent Application Laid-Open No. 8-339346.
In the bus arbiter described in Japanese Patent Laid-Open Publication No. H11-235, the maximum time of bus use is specified by time data set in the wait set register, and until the maximum time is reached,
The bus is occupied and connection requests from other bus masters
Mask by a mask circuit. When the maximum time is exceeded, the bus arbiter does not lose the effect of the mask circuit and permits switching in response to a request to another bus master.

FIG. 6 is a diagram showing the configuration of the wait control circuit 610 of the bus arbiter, which comprises a wait set register 620, a timer 630, and a mask circuit 640. The mask circuit 640 includes an 8-bit arbiter 6
Monitoring eight REQ inputs (REQA-REQH) and eight GNT outputs (GNTA-GNTH)
When both the REQ and the corresponding GNT are activated, a start signal is generated, and the timer 630 starts counting. During a wait period until the count output of timer 630 becomes "0", mask circuit 640 provides an 8-bit arbiter for other masters as long as REQ from the master currently holding the GNT is active. Mask the REQ input to 600. As a result, even if a REQ is generated from a bus master having a higher priority than the master currently holding the GNT, it is possible to prevent the GNT from being switched.

When the count output becomes "0", the wait period ends. At this time, the mask circuit 640 masks the REQ input from the bus master that has been held so far and invalidates the mask of the REQ input from another bus master. Therefore, the PCI bus can be released from the master having the GNT during the wait period, and the right to use the bus can be given to another bus master.

[0010]

However, in the case where data is read from the main storage device even though the bus is occupied, a long waiting time is required, and the occupation time is reached before the first data is transferred. As a result, the bus may be released without executing the scheduled data transfer. In this case, it is necessary to acquire the bus again to occupy the bus, and as a result, there is a problem that data cannot be transferred efficiently.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide an input / output control method and apparatus capable of efficiently transferring data.

[0012]

An input / output control method according to the present invention operates as a bus master in an information processing system and has a bus occupation time. The method further comprises a step of counting the waiting time, and delaying the counted waiting time to notify a timeout of the bus occupation time.

According to the input / output control method of the present invention, the input / output control method which operates as a bus master in an information processing system and has a bus occupation time counts a waiting time until the first data is transferred. And a notification step of notifying a timeout of the bus occupation time with a delay of the counted waiting time.

Further, the notifying step of notifying the timeout includes a second timing step of notifying the timeout when the first data is not transferred even after the lapse of twice the bus occupation time.

Next, the input / output control device of the present invention operates as a bus master in the information processing system, and in the input / output control device having the bus occupation time, the waiting time until the first data is transferred is reduced. There is provided a means for counting and delaying the counted waiting time to notify the timeout of the bus occupation time.

Further, the input / output control device of the present invention operates as a bus master in an information processing system, and counts a waiting time to be transferred until the first data is transferred in the input / output control device having a bus occupation time. And a timeout detection delay circuit for notifying a timeout of the bus occupation time with a delay of the counted waiting time.

Further, the timeout detection delay circuit has a second waiting time counter for notifying a timeout when the first data is not transferred even after lapse of twice the bus occupation time.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of the input / output control device of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an information processing system to which the input / output control device of the present invention is applied. FIG. 2 is a time chart showing the timing of the input / output control device of the present invention.

Referring to FIG. 1, an information processing system to which an input / output control device according to an embodiment of the present invention is applied,
It includes a system bus 160 and an input / output bus 170. The system bus 160 includes a central processing unit 110,
The main storage device 120 is connected. A plurality of input / output control devices 150 are connected to the input / output bus 170. A bus connection device 130 is connected between the system bus 160 and the input / output bus 170 bus. I / O bus 17
A bus control device 140 for monitoring this is connected to 0.

The central processing unit 110 is a device that performs processing such as various operations, and has a role of issuing input / output instructions. The main storage device 120 stores commands to be executed and data to be input / output commands. The main storage device 120 sends data on the system bus 160 in response to a memory read request from the central processing unit 110 or the bus connection device 130, and stores the data on the system bus 160 at the specified address in a memory write request. I do. The bus connection device 130 connects the system bus 160 and the input / output bus 170 to each other, and performs protocol conversion and the like.

The input / output control device 150 connects an input / output device (not shown). The input / output control device 150 also has a bus master timer register 154 that stores therein a preset value set as a bus occupation time, a bus master timer counter 153 that counts the time during which the bus master is operating, and operates as a bus master. A waiting time counter 155 for counting the time waited until the first data is transferred, and a bus master timer counter 15.
3 and the bus mass timer register 154 detect a match, and a time-out detection delay circuit 152 for delaying the time counted by the waiting time counter 155 and notifying a time-out, and terminating the data transfer by the notification of the time-out detection delay circuit 152 I / O interface circuit 1
51.

The system bus 160 has an address line, a data line, and a control line, and is used for exchanging signals between the central processing unit 110, the main storage unit 120, and the bus connection unit 130. The input / output bus 170 is a system bus 1
As in the case of the I / O control device 150, it has an address line, a data line, and a control line, transfers data between the main storage device 120 and the I / O control device 150, and transfers data from the central processing unit 110 to the I / O control device 150. Used to issue I / O instructions.

Next, the operation of the input / output control device 150 of the present invention will be described in detail with reference to FIGS.

Referring to FIG. 1, input / output controller 150
Acquire the right to use the bus and start operating as a bus master. The time is defined as t ₀ in FIG. At the same time, the bus master timer counter 153 starts counting the bus occupation time (c in FIG. 2). Similarly, the waiting time counter 155
Is the time t ₁ from the start of the operation of the data read instruction to the start of the transfer of the first data, including the measurement of the waiting time.
Is counted (d in FIG. 2).

When the count time of the bus master timer counter 153 reaches the bus occupation time t ₂ preset in the bus master timer register 154, the timeout detection delay circuit 152 detects that the two times coincide. Then, the timeout detection delay circuit 152 notifies a timeout t ₃ output interface circuit 151 is delayed by time t ₁ which is counted in the latency time counter 155 (e in FIG. 2).

The input / output interface circuit 151 extends the bus occupation time of the bus master in response to the notification from the timeout detection delay circuit 152 and ends the data transfer time (a in FIG. 2).

Here, as shown in FIG. 2B, if the transfer data has a data length that is completed within the initially set bus occupation time t ₂ , the transfer data is delayed by the time t ₁ counted by the waiting time counter 155. If the bus occupation time of the bus master is extended, processing is performed by one transfer (t _{4 in} FIG. 2).

If the transfer data has a data length equal to or longer than the initially set bus occupation time t ₂ , the transfer data can be transferred by the number of times divided by the initially set bus occupation time t _2. it can.

Next, a case where the input / output control device releases the right to use the bus due to a failure will be described. FIG. 3 is a block diagram for releasing a bus use right due to a data transfer failure.

After the I / O controller 150 acquires the right to use the bus and starts operating as a bus master, the waiting time counter 155 sets the time t ₁ from the start of the operation of the data read instruction to the start of the transfer of the first data. Count. However, when the first data is not transferred from the bus master even after the elapse of the bus occupation time, the timeout detection delay circuit 152 must notify the input / output interface circuit 151 of the timeout. Therefore, the waiting time counter 1 is provided inside the timeout detection delay circuit 152.
56 are provided.

When the waiting time counter 156 counts, for example, twice as long as a preset bus occupation time, it determines that a hardware failure or software runaway has occurred, and a time-out is sent to the input / output interface circuit 151 at that time. Notice.

Next, another embodiment of the present invention will be described with reference to the drawings.

FIG. 4 is a block diagram showing another configuration of the information processing system to which the input / output control device of the present invention is applied.

In the embodiment of FIG. 1, the central processing unit 11
0 and the main storage device 120 were connected via a system bus 160 and a bus connection device 130 to an input / output bus 170 to which an input / output control device 150 was connected. However, the input / output control device 450 of FIG. 4 includes the central processing unit 410 and the main storage device 42 when connected to the system bus.
0 and the input / output controller 440 are connected to the same common bus 460.

[0036]

According to the present invention, the occupation time of the bus reaches before the first data is transferred, and the bus is not released without executing the data transfer. There is an effect that data can be efficiently transferred to and from the device.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an information processing system to which an input / output control device of the present invention is applied.

FIG. 2 is a time chart showing the timing of the input / output control device of the present invention.

FIG. 3 is a block diagram for releasing a bus use right due to a data transfer failure.

FIG. 4 is a block diagram showing another configuration of the information processing system to which the input / output control device of the present invention is applied.

FIG. 5 is a block diagram illustrating a configuration of an information processing system to which a conventional input / output control device is applied.

FIG. 6 is a block diagram showing a configuration of another conventional input / output control device.

[Explanation of symbols]

 110, 410 Central processing unit 120, 420 Main storage device 130, 430 Bus connection device 140, 440 Bus control device 150, 450 I / O device 151, 451 I / O interface circuit 152, 452 Timeout detection delay circuit 153, 453 Bus master timer counter 154, 454 Bus master timer register 155, 156, 455 Wait time counter 160 System bus 170 I / O bus 460 Common bus

Claims (6)

(57) [Claims] 1. An input / output control method which operates as a bus master and has a bus occupation time in an information processing system, wherein a waiting time until a first data is transferred is counted, and the waiting time is delayed by the counted waiting time. And notifying a timeout of the bus occupation time. 2. An input / output control method which operates as a bus master and has a bus occupation time in an information processing system, comprising: a first time counting step for counting a waiting time until a first data is transferred; An input / output control method comprising a notification step of notifying a timeout of a bus occupation time with a delay of a given waiting time. 3. The method according to claim 2, wherein the notifying step for notifying the timeout includes a second notifying step for notifying the timeout when the first data is not transferred even after a lapse of twice the bus occupation time .
3. The input / output control method according to claim 2, further comprising: 4. An input / output control device which operates as a bus master and has a bus occupation time in an information processing system, counts a waiting time until the first data is transferred, and delays by the counted waiting time. An input / output control device for notifying a timeout of a bus occupation time. 5. An input / output control device which operates as a bus master and has a bus occupation time in an information processing system, a first waiting time counter for counting a waiting time until the first data is transferred, An input / output control device comprising a timeout detection delay circuit for delaying the bus occupation time by delaying by the counted waiting time. 6. A time-out detection delay circuit for notifying a time-out when the first data is not transferred even after a lapse of twice the bus occupation time .
The input / output control device according to claim 5, further comprising a waiting time counter.