JP2001243170A - Data transfer device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data transfer device which enables to enhance usage efficiency of a CPU bus and an internal bus of an image processing device, and to reduce hardware of CPU interface in the image processing device. SOLUTION: This data transfer device is composed such that IO access data on a host bus 3 connecting a host CPU 1 and an image processing device 40 is transferred, on an internal local bus 20 of the image processing device 40 by DMA transfer system to a memory 27 via a memory interface 23. A write buffer 19 in a data transfer device 30 stores continuous address access data temporarily and transfers it by DMA by one operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer device having a write buffer, and more particularly to a host bus connecting a CPU and an image processing device, and a UGM (Unified Memory) as a work memory of the image processing device. The present invention relates to a data transfer device that can effectively use both buses in an image processing system.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing a conventional system in which data transfer is performed. Host bus 3
The host CPU 1, the main memory 2, and the image processing device 40 are connected thereto. The image processing device 40
It is composed of multiple blocks. 30a is a data transfer device, 31 is an image generator, 32 is an image input device, 33 is an image output device, 23 is a memory interface, and 26 is a local bus arbiter. The local bus 20 of the conventional data transfer system includes an address bus and a data bus.

The operation of the data transfer system shown in FIG. 6 will be described briefly. The host CPU 1 roughly performs two processes.

The first process is data generation and data transfer for image processing. Preprocessing of data processed by the image processing device 40 is performed by a software program of the host CPU 1, and the data is temporarily transferred to the main storage memory 2. When the data for image processing has been prepared in the unit capacity, the host CPU 1 performs IO transfer via the image processing device 40,
The image processing data is transferred to the memory 27.

A description will be given focusing on the image processing apparatus 40.
In response to the IO transfer access from the host CPU 1, the data transfer device 30a temporarily holds the image processing data and requests the local bus arbiter 26 to permit the use of the local bus 20. With the permission to use the local bus 20, the image processing data temporarily stored in the memory interface 23 is output, and the memory interface 23 outputs the image processing data to the memory 27.

The second process is control of the image processing device.
After transferring the image processing data to the memory 27, the host CPU 1 issues an image generation start activation command to the image generator 31. Accordingly, the image generator 31 requests the local bus arbiter 26 to use the local bus, obtains the local bus use permission, and obtains the memory interface 23.
, The image processing data is read out from the memory 27 to perform the image generation processing. Thereafter, the local bus arbiter 26 is again requested to permit the use of the local bus 20, and the local bus 20 is permitted to be used, and the image generation data is written to the memory 27 via the memory interface 23. The image generator 31 stores the image processing data in the memory 2.
When the number decreases to 7, the host CPU 1 is interrupted,
The host CPU 1 again uses the data transfer device 40
The next image processing data is transferred. In the image processing device 40, in addition to the operation of the image generator 31, the image input device 32
An output synchronizing signal and an external video output signal are input from the external video 34, an image input process is performed, and at the same time, the local bus arbiter 26 is periodically requested to use a local bus, and the local bus 20 is used. The image input processing data is written to the memory 27 via the memory interface 23.

The image output unit 33 periodically requests the local bus arbiter 26 for permission to use the local bus in accordance with the monitor display synchronization signal, obtains the permission to use the local bus 20, and outputs the memory via the memory interface 23. The image generation data and the image input data stored in the memory 27 are read and output to the monitor 35 after the display processing.

As described above, part of the image processing data used by the image processing device 40 is transferred from the main memory 2 to the memory 27 via the host bus 3 and the local bus 20 by the host CPU 1. You. Further, the local bus 20 is used in a time-division manner by a plurality of internal blocks in accordance with data processing inside the image processing device 40.

The amount of image processing data handled by the image processing device 40 increases in proportion to the display size of the monitor 35 connected to the image output device 33. Recently, 1280 dots x
It is not uncommon to handle enormous amounts of data, such as handling natural images with a display size of 1024 dots. In order to realize such a display size, the host CPU 1
It is necessary to speed up the transfer of image processing data from the server. The local bus 20 in the image processing device 40 is an LSI internal bus, and generally, the local bus clock can be operated at a higher speed than the host bus clock.

However, as described above, the memory 27
Is shared by a plurality of blocks in the image processing apparatus 40. Therefore, when the access right of the local bus 20 is acquired at the time of data input / output from the host CPU 1 and data transfer is performed by the host bus clock, the use of the local bus Efficiency is reduced.

Therefore, the transfer data from the host CPU 1 is temporarily held in a write buffer in the data transfer device 30, and the data transfer from the data transfer device 30a to the memory 27 is performed at a local bus clock rate. I have.

FIGS. 7 and 8 show timings of data transfer using the host bus 3 and the local bus 20 in the conventional data transfer device.

The case where the data transfer device 30a includes a write access buffer will be described. In the case of a write access from the host CPU 1, an address and data are output to the host bus 3 together with a write access signal in synchronization with the host bus clock. The write buffer has an address field and a data field. If the capacity of the write buffer is set to four accesses with the upper limit of the buffer capacity, the write access to the order 1 to 4 is performed without generating a wait signal to the host CPU 1. Access is possible. When there is untransferred data in the write buffer, the data transfer device 30a performs a bus use request cycle r1 with the local bus arbiter 26. As a result, when the local bus 20 is in a state where it can be used immediately, the data transfer device 30a sends the data to the local bus 20 in synchronization with the local bus clock.
The address and data for one access held in the write buffer are output, and the memory interface 23
Writes these data in the memory 27. As described above, the data transfer device 30a can simultaneously perform the write access from the host CPU 1 and the output to the local bus 20. For each bus use request of the local bus 20, one access temporarily held in the write buffer is transferred on the local bus 20. Since the access data is sequentially read from the write buffer and becomes writable, it is not necessary to generate a wait signal to the host CPU 1 for the write access in order 5 and order 6.

The local bus 20 of the data transfer device 30a
Is generally lower in priority than another block in the image processing apparatus. For example, the image output device 33 transmits the monitor output data to the local bus 2 by an external synchronization signal.
It is necessary to read from the memory 27 using 0. Therefore, if other blocks use the local bus for a long time,
Because the output data of the monitor 35 cannot be prepared,
The screen drops out. For this reason, other blocks have to perform data transfer of the unit transfer size. Accordingly, the data transfer device 30a performs one write access transfer from the CPU 1. Although it is conceivable to perform transfer on the local bus collectively with the upper limit of the write buffer capacity, the control when reading and writing from the write buffer are performed simultaneously is more complicated than in this example. Also, local buses 20 from other blocks
When there is a request to use the local bus 20, or when another block uses the local bus 20, the data transfer device 3
0a is the local bus 2 from the local bus arbiter 26
The cycle (for example, r2) for obtaining the use permission of 0 may extend over a plurality of cycles. Conversely, the data transfer device 30a
, The data processing of another block is temporarily suspended.

In the case of the access in the order 7, the use permission of the local bus 20 cannot be obtained immediately. Therefore, the data temporarily stored in the write buffer becomes the upper limit, and the wait signal is output to the CPU 1.

Thereafter, write accesses from order 8 to order 13 are similarly performed.

Note that data transfer from the write buffer to the local bus may be performed in units of the write buffer capacity. In this case, a write access from the host CPU to the number of words of the write buffer capacity is premised. Japanese Patent Application Laid-Open No. 6-274450 discloses the fixed-length data transfer in detail, and discloses that if the number of access words is smaller than the write buffer size, it is necessary to perform extra write access. I have.

[0018]

However, the above prior art has the following problems.

First, as a write buffer in the data transfer device 30a, it is necessary to provide fields for data and address in IO transfer from the host CPU 1, and when the buffer size is limited due to a chip cost problem, The number of accesses of the host CPU 1 that can be temporarily held is restricted by the upper limit of the buffer size.

Second, a data bus and an address bus are required as local buses.

Third, when local bus access is performed depending on the presence / absence of temporarily stored data in the write buffer, a local bus use request frequently occurs, and the processing speed of other blocks using the local bus is reduced.

Fourth, when performing local bus access using write data of the upper limit of the write buffer capacity, the total number of write access words from the host CPU must be an integral multiple of the write buffer capacity. Low versatility.

The present invention improves the efficiency of use of a CPU bus and an internal bus of an image processing apparatus,
It is an object of the present invention to provide a data transfer device capable of reducing interface hardware.

[0024]

In order to solve the above-mentioned problems, a data transfer device according to the present invention provides an address and data which are transferred by the CPU via the first bus for each access.
A data transfer device for transferring data to a locally used memory via a second bus, comprising: an address determination unit;
The system includes a write buffer, a buffer amount determination unit, an access control unit, and a parameter generation unit.

The address discriminating means holds the address output by the CPU at the time of write access via the first bus at each access, and compares the access with the address of the previous access to detect a continuous address. The write buffer continuously holds the data output from the CPU when the address determination means determines that the address access is continuous, with the data capacity as an upper limit. The buffer amount determining means includes:
It outputs information on the data capacity held by the write buffer. The access control means, when notified by the buffer amount determination means that there is no write capacity in the write buffer at the time of the write access by the CPU, or when the address determination means detects a discontinuous address access and stores the DMA untransferred data in the write buffer. Or if there is a CP
Detects read access from U and sends DM to write buffer
When there is untransferred data, a wait signal to the CPU is generated. The parameter generation unit generates a DMA transfer parameter corresponding to the write access temporarily stored in the write buffer. The data held in the write buffer is output by DMA transfer via the second bus.

According to this configuration, since the data transfer on the local bus is performed by the DMA transfer, the IO access can be converted into the DMA transfer of the continuous address unit. As a result, even a general CPU that does not have a built-in DMA controller or the like can use a high transfer rate D on a local bus.
MA transfer can be performed.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION An entire system in which data is transferred using a data transfer device according to an embodiment of the present invention is the same as that shown in the block diagram of FIG.
FIG. 1 shows the internal configuration and peripheral connections of the data transfer device 30 in a system using the data transfer device 30 of the present embodiment instead of the conventional data transfer device 30a in FIG.

In FIG. 1, 1 is a host CPU, 2 is a main memory, 3 is a host bus, 20 is a local bus,
23 is a memory interface, and 27 is a memory.

The data transfer device 30 includes a continuous address detecting means 4, a DMA transfer parameter sending means 7, a controller 1
1, a buffer control means 15 and a write buffer 19 capable of temporarily storing four accesses. The continuous address detecting means 4 includes a register 5 and a comparator 6. D
The MA transfer parameter sending means 7 includes a register 8, a parameter output device 9, and a counter 10. The buffer control means 15 includes a write pointer generator 16, a comparator 1
7 and a read pointer generator 18.

The memory interface 23 includes a register 24, an interface 25, and an arbiter 26. 12 indicates a read access signal, 13 indicates a wait signal, and 14 indicates a write access signal. Reference numeral 21 denotes a local bus use request signal, and reference numeral 22 denotes a local bus use permission signal. The local bus in the present invention is constituted by a data bus.

The comparator 6 compares the previous access address output from the register 5 with the current access address, and outputs 1 if the address is a continuous address and 0 if the address is a discontinuous address.

The comparator 17 includes a write pointer generator 16
Is compared with the output of the read pointer generator 18. If there is no data to be transferred to the memory 27 in the write buffer 19, the flag 00 is stored in the
If there is untransferred data to the memory 7 and writing is possible, the flag 01 is output to the controller 11 if the write buffer 19 cannot write because the amount of untransmitted data to the memory 27 is large. .

The controller 11 detects the assertion of the write access signal 14 or the read access signal 12 and outputs the following output according to the output signal of the comparator 6, the output signal of the comparator 17, the output signal of the arbiter 22, and the internal state. Signal control is performed simultaneously or sequentially according to the internal synchronization signal.

In the first control, the write pointer generator 16 generates a write pointer. As a result, the write buffer 19 temporarily holds the write data on the host bus 3 in the buffer line indicated by the write pointer.

In the second control, a write enable signal is output to the register 5. This allows register 5
Temporarily holds the address of the host bus 3.

In the third control, a write enable signal is output to the register 8. This makes register 8
Temporarily holds the address information output from the register 5.

In the fourth control, the counter 10 is initialized. In this case, the initial value is 1.

In the fifth control, the output of the counter 10 is increased by one.

In the sixth control, when the local bus use permission signal 22 is input from the arbiter 26, the parameter output unit 9 outputs the output of the register 8 and the parameter indicating the word number DMA write indicated by the counter 10 to the parameter output unit 9.
Output to the register 24.

In the seventh control, the read pointer generator 18 generates a read pointer. Thereby, the write buffer 19 outputs the data of the buffer line indicated by the read pointer to the local bus 20.

In the eighth control, when the flag 10 is input from the comparator 17, or when the flag 01 is input from the comparator 17 and 0 is input from the comparator 6, the arbiter 26 uses the local bus. The request signal 21 is output.

In the ninth control, when the flag 10 is input from the comparator 17 and the assertion of the write access signal 14 is detected, or when the flag 17 is
When 1 is input and 0 is input from the comparator 6, or the comparator 17 outputs the flag 01 or the flag 10
Is input, and when a read access is performed from the host CPU 1, the access wait signal 1 is transmitted to the host CPU 1.
3 is output.

In the tenth control, the host CPU 1
The read access signal 12 is input and the comparator 17
When the flag 00 is input, the output of the address on the host bus 3 and the one-word D
The register 24 outputs a parameter indicating MA read.

FIGS. 2 and 3 are diagrams showing the timing of data transfer using the host bus 3 and the local bus 20 in the data transfer device 30. FIG. The data transfer device 3 according to the present embodiment will be described with reference to FIGS.
The operation of 0 will be described.

The host CPU 1 stores image processing data in the memory 2, and the image processing data is transferred to the memory 27 via the data transfer device 30. At the start of data transfer, the write pointer generator 16 and the read pointer generator 18 have been initialized.

At the time of write access in order 1, the host CP
U1 asserts the write access signal 14 and outputs write data to the host bus 3. Controller 1
1 causes the buffer data indicated by the write pointer of the write pointer generator 16 in the write buffer 19 to temporarily hold the write data a1 on the host bus 3 under the first control. Further, the second control causes the register 5 to temporarily hold the address of the host bus 3.
Further, the third control causes the register 8 to temporarily hold the address information output from the register 5.

At the time of the write access of the order 2, since the addresses are continuous, the controller 11 performs the same control as at the time of the write access of the order 1, and the write buffer 19 temporarily holds the write data a2. . Further, the register 5 temporarily holds the address of the host bus 3 under the second control.

At the time of the write access of the order 3, since the addresses are continuous, the controller 11 performs the same control as at the time of the write access of the order 1, and the write buffer 19 temporarily holds the write data a3. Further, the register 5 temporarily holds the address of the host bus 3 under the second control.

At the time of the write access of the order 4, since the addresses are continuous, the controller 11 performs the same control as at the time of the write access of the order 1, and the write buffer 19 temporarily holds the write data a4. . In this case, untransferred data to the memory 27 is accumulated in the write buffer 19, and the remaining capacity is exhausted. For this reason, the controller 11
Starts preparation for transfer to the memory 27 (r
1).

Next, from the arbiter 26 to the local bus 20
When the use permission signal 22 is input, the DMA transfer parameters are transferred to the memory interface 2 by the sixth control.
3 (p1), and then, by the seventh control, the data stored in the write buffer 19 is DMA-transferred to the memory interface 23 via the local bus 20. The memory interface 23 writes data to the memory 27. As a result, the write access data stored in the write buffer 19 disappears. During this time, as shown in the order 5, when the next write access of the host CPU 1 is performed, a wait is applied to the host CPU 1 by the ninth control. The comparator 17 outputs the flag 00 to the controller 11, and as soon as the DMA transfer is completed and the untransferred data in the write buffer 19 is exhausted, the controller 11 performs the first control. The upper write data a5 is temporarily held in the buffer line indicated by the write pointer. Further, the register 5 temporarily holds the address of the host bus 3 under the second control. Further, the register 8 temporarily holds the address information output from the register 5 under the third control.

In steps 6 to 8, the same operations as in steps 2 to 4 are performed.

Further, in the order 9 and the order 10, the same operation as the order 5 and the order 6 is performed.

At the time of write access in the order 11, since the addresses are discontinuous, the controller 11
After giving a wait to the write access of the host CPU 1, preparation for transfer to the memory 27 is started by the eighth control (r3). Next, from the arbiter 26 to the local bus 20
When the use permission signal 22 is input, the DMA transfer parameters are transferred to the memory interface 2 by the sixth control.
3 (p3), and then, by the seventh control, DMA transfer the data stored in the write buffer 19 to the memory interface 23 via the local bus 20. The memory interface 23 writes data to the memory 27. As a result, the write access data stored in the write buffer 19 disappears. The comparator 17 outputs a flag 00 to the controller 11, and the DMA transfer is completed.
Performs the first control, and the write buffer 19 temporarily holds the write data b1 on the host bus 3 in the buffer line indicated by the write pointer. The register 5 temporarily holds the address of the host bus 3 under the second control. Further, under the third control, the register 8 temporarily holds the address information output from the register 5.

In the order 12 and the order 13, the same operation as the order 1 to the order 2 is performed.

The access in order 14 is a read access. As an example, a case where a control register inside the data transfer device 30 is read is shown. Since the data is internal to the data transfer device, the local bus 20 is not used. The controller 11 waits for the read access of the host CPU 1 under the ninth control, and then starts preparation for transfer to the memory 27 under the eighth control (r4). Next, when the local bus 20 use permission signal 22 is input from the arbiter 26, the sixth control sends the DMA transfer parameter to the memory interface 23 (p4), and then the seventh control.
Of the data stored in the write buffer 19 to the memory interface 23 via the local bus 20 under the control of D.
MA transfer and the memory interface 23
Write data to Thereby, write buffer 1
The write access data stored in No. 9 disappears. The comparator 17 outputs the flag 00 to the controller 11 and negates the access wait signal to the CPU 1 as soon as the DMA transfer is completed and the untransferred data in the write buffer 19 runs out. When the read access is to the memory 27, the tenth control outputs the read access data to the CPU 1 by DMA transfer of one word from the memory 27 and negates the access wait signal to the CPU 1.

The efficiency of write access to the host bus 3 can be increased by the configuration of the write buffer.

As another embodiment in which the above data transfer device is modified, double write control can be performed using two write buffers 19. FIG. 4 and FIG.
FIG. 3 is a diagram showing timing of data transfer using the host bus 3 and the local bus 20 in that case. In this way, order 5 and order 9 in FIG. 2 and order 11 in FIG.
Host DMA during DMA transfer on the local bus
Write access from U1 can be performed simultaneously.
This makes it possible to reduce the period for generating waits for the host CPU 1.

[0058]

According to the present invention, the write data from the host CPU performing the IO access transfer on the host bus is
When transferring image data to a memory (unified memory) used locally by the image processing apparatus via a local bus, the IO access is transferred to a continuous address unit in order to perform data transfer on the local bus by DMA transfer. The data transfer device is configured to perform the conversion.

As a result, even a general CPU without a built-in DMA controller or the like can perform a DMA transfer with a high transfer rate on the local bus. in this case,
An address field is not required as a write buffer in the data transfer device, and the amount of hardware can be reduced. Further, an address bus is not required as a local bus of the data image processing apparatus. Further, by controlling the DMA transfer of the data in the write buffer to the local bus by the read access from the host CPU, the CP is controlled.
The sequentiality of data access can be guaranteed by the U program.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an internal configuration and peripheral connections of a data transfer device according to an embodiment of the present invention;

FIG. 2 is a diagram showing data transfer timing in the data transfer device of FIG. 1;

FIG. 3 is a diagram showing the timing of data transfer following FIG. 2;

FIG. 4 is a diagram showing data transfer timing in a data transfer device using double buffer control according to another embodiment of the present invention;

FIG. 5 is a diagram showing the timing of data transfer following FIG. 4;

FIG. 6 is a block diagram showing a system in which data transfer is performed in a conventional example.

FIG. 7 is a diagram showing data transfer timing in a conventional data transfer device.

FIG. 8 is a diagram showing the timing of data transfer following FIG. 7;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Host CPU 2 Memory 3 Host bus 5 Register 6 Comparator 9 Parameter output device 16 Write pointer generator 18 Read pointer generator 19 Write buffer 20 Local bus 26 Local bus arbiter 27 Memory 30, 30a Data transfer device 31 Image generator 32 Image input device 33 Image output device

Claims (1)

[Claims] 1. A data transfer device for transferring, via a second bus, an address and data to which a CPU performs I / O transfer for each access via a first bus to a memory used locally, Address determining means for holding the address output by the CPU at the time of write access via the bus at each access, and comparing the access with the address of the previous access to detect a continuous address; A write buffer that continuously holds data output from the CPU when the access is determined, with a data capacity as an upper limit; a buffer amount determination unit that outputs information on a data capacity held by the write buffer; At the time of access, the write capacity of the write buffer is reduced by the buffer amount determination means. DM on the detected write buffer when the case or said address discrimination means has been notified is DMA untransmitted data to detect and the write buffer discontinuous address access or a read access from the CPU that
A: when there is untransferred data, access control means for generating a wait signal for the CPU; and a parameter generation unit for generating a DMA transfer parameter corresponding to write access temporarily held in the write buffer; A data transfer device for outputting data held in a buffer by DMA transfer via the second bus.