JPH0644179A - Data transfer controller - Google Patents

Abstract

PURPOSE:To realize a data transfer controller improved in data transfer rate and data throughput. CONSTITUTION:A DMAC 5 is provided with address counters 5A and 5B, a number of words counter 5C, a judging part 5D, and bus control parts 5E and 5F. The data of the prescribed number of words is stored in a buffer memory 6 from a memory 2 or 4, and this data of the prescribed number of words is transferred to the memory 2 of 4. A monitor circuit 7 is provided with a counter 7A and a control part 7B. The counter 7A counts the data to be inputted and outputted to/from the buffer memory 6, and the control part 7B controls the operation of the buffer memory 6 by the command of the judging part 5D. At the time of data transfer between the memory 2 and the buffer memory 6, a bus for the MPU 3 of the memory 4 is released, and at the time of the data transfer between the memory 4 and the buffer memory 6, the bus for the MPU 1 of the memory 2 is released.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA controller (Direct Memory Access controller) for transferring data from a memory subordinate to each of a plurality of microprocessors to the memory.
oller) and other data transfer control devices.

[0002]

2. Description of the Related Art In a multiprocessor system, there is a DMA controller that transfers data from a memory that is dependent on one microprocessor to a memory that is dependent on another microprocessor without going through the microprocessor. FIG. 5 is a schematic configuration diagram of the DMA control device.
In FIG. 5, 1 and 3 are microprocessors (MP
U), 2 is the memory of MPU 1, and 4 is the memory of MPU 3. Reference numeral 80 is a DMA controller (DMAC), and this DMAC 80 is provided with address counters 81 and 82 and a transfer word number counter 83. The address counter 81 is for designating the transfer source address, and the address counter 82 is for designating the transfer destination address. FIG. 6 is a timing chart of bus arbitration (arbitration of data bus right) and memory access of the DMAC 80. 5 and 6, the memory 2 of the MPU 1 to the memory 4 of the MPU 3
The case of transferring data will be described below. First, MPU1
After setting the address counter 81, the address counter 82, the transfer word number counter 83, and the operation mode (cycle still mode or burst mode described later) to the DMAC 80, the DMA transfer is activated. DM
When the A transfer is activated, the DMAC 80 starts a bus right acquisition operation (bus arbitration) for the MPU 1. As the procedure of bus arbitration, first, as shown in FIG. 6A, at time t0, the bus request signal BR1 is supplied to the MPU1 and DM is sent to the MPU1.
Requests release of bus right for A transfer. This BR
The MPU 1 supplied with the 1 signal releases the bus right and supplies the bus response signal BA 1 indicating this to the DMAC 80 ((B) of FIG. 6). Then, the DMAC 80 uses the memory 2
On the other hand, the contents of the address counter 81 are output as a memory address and a data read signal (RSTB
Signal) (at times t in (C) and (D) of FIG. 6)
1) Start the data read operation.

When data is output from the memory 2, DM
AC80 stores the data internally and RST
The B signal is negated, that is, invalidated (time t2 in FIG. 6D), and the address counter 81 is updated. After reading the data from the memory 2, the MPU 3
The bus request signal BR2 is supplied in the same manner as 1 ((E) in FIG. 6).
At time t3), the bus arbitration is started for MPU3 as well as MPU1. And DMAC8
When 0 is supplied with the bus response signal BA2 from the MPU 3 ((F) in FIG. 6), the address counter 8 for the memory 4
The contents of No. 2 are output as the address of the memory 4 ((G) of FIG. 6), and the data fetched in the DMAC 80 is output as the write data. Then DMAC8
0 supplies the memory write signal (WSTB signal) to the memory 4 (time t4 in (H) of FIG. 6) to transfer data to the memory 4. After the data transfer to the memory 4 is completed, D
The MAC 80 negates the WSTB signal, updates the address counter 82, and decrements the transfer word number counter 83.

If the above-mentioned DMA transfer is the burst mode transfer, the DMAC 80 continues to supply the bus request signals BR1 and BR2 to the MPU1 and MPU3,
The bus is not released, and data transfer is continuously executed until the content of the transfer word number counter 83 becomes "0". Figure 7
FIG. 9 is a timing chart when the DMA transfer is a burst mode transfer. In FIG. 7, the bus request signal BR
1 and BR2 are MPU1 and MPU3 from time t0 to time t4.
To the bus response signals BA1 and BA2 at time t1.
It is supplied to the DMAC 80 from t5 to t5. And time t
The transfer of one data is completed from 2 to t3. Therefore, the data transfer is repeated between the times t2 and t4, and the transfer of all the data is completed.

On the other hand, in the cycle still mode transfer, the DMAC 80 once negates the bus request signals BR1 and BR2 each time one data is transferred, and the MPU
1. Open the bus for MPU3. Then, arbitration is repeated for each data, and the data transfer is executed until the content of the transfer word number counter 83 becomes "0". FIG. 8 is a timing chart when the DMA transfer is the cycle still mode transfer.
In FIG. 8, the bus request signal BR1 changes to M at time t0.
The bus response signal BA1 is supplied to PU1 at time t1.
Are supplied to the DMAC 80. Then, at time t2,
The data read signal RSTB is supplied to the memory 2 to start reading data. Next, at time t3, the bus request signal BR2 is supplied to the MPU3. Subsequently, at time t4, the bus response signal BA2 is supplied to the DMAC 80, the memory write signal WSTB is supplied to the memory 4, and the writing of data is started. And time t
At 5, the transfer of one data is completed, and at time t6, the transfer of the next one data is started in the same manner as described above.

As examples similar to the above-mentioned data transfer control device, Japanese Patent Laid-Open Nos. 60-158849, 61-168003 and 62-2128 are available.
There is one described in Japanese Patent Publication No. 84.

[0007]

However, the above-mentioned conventional data transfer control device has the following problems. First, when the burst mode transfer is performed, the transfer time for one piece of data is one arbitration (from time t0 to t1 in FIG. 7), so the data transfer cycle. The time is the total time of the reading period of the memory 2 and the writing period of the memory 4 (see FIG.
From time t2 to time t3). Therefore, the data transfer rate in the burst mode transfer is higher than that in the cycle still mode transfer in which arbitration is performed for each data transfer. However, the bus right for the memories 2 and 4 is occupied by the DMAC 80 during the data transfer period (time t0 to t5 in FIG. 7). Therefore, during the data transfer period, MPU1 and MPU3
Cannot access the memories 2 and 4, and cannot perform data processing on the memories 2 and 4. Therefore, during the data transfer period, MPU1 and MP
The memories that U3 can access are memory 2 and memory 4.
However, the data processing capacity was reduced.

On the other hand, in the case of cycle still mode transfer,
The bus right of the memories 2 and 4 is released to the MPU 1 and MPU 3 each time the transfer of one data is completed. In other words, by cycle still mode transfer,
When data is transferred from the memory 2 to the memory 4, for example, the DMAC 80 acquires the bus right for the memory 4 only for the time required for actual data writing (time t4 to t5 in FIG. 8). Become. Therefore, MPU3
While the MAC 80 is reading data from the memory 2 (time points t2 to t4 in FIG. 8), the bus right to the memory 4 can be obtained, and the data processing capability of the MPU 3 is not significantly reduced (MPU1 Is the same as MPU3).

However, in the cycle still mode transfer, the arbitration is executed for each data transfer and the bus right acquisition operation is executed. Therefore, the data transfer is slower than the burst mode transfer. Met. In particular, one of the memories used is DRAM (Dynamic Random Access Memory).
In the case of a low-speed memory such as y), even if the other memory can be accessed at a high speed, the transfer speed must be adapted to a DRAM having a low access speed, which results in a low speed. In the case of the cycle still mode transfer, the data
Since the bus arbitration is performed every time the data transfer is performed and the bus right is acquired, the high speed memory access using the burst mode access described later is impossible. An object of the present invention is to realize a data transfer control device having improved data transfer speed and data processing capacity.

[0010]

In order to solve the above problems, the present invention is constructed as follows. A first-in first-out data buffer memory for storing the transfer data from the storage means, a buffer memory monitoring circuit for monitoring the degree of data storage of the data buffer memory and controlling the data input / output of the data buffer memory, and each of the storage means. Arbitration of the data bus right and outputting the address of the data to be transferred to the storage means, and the buffer memory monitoring circuit, when it is detected that the data can be stored in the data buffer memory. Instructs the storage means of the transfer source and the buffer memory monitoring circuit to store the data in the data buffer memory from the storage means of the transfer source, and the data is stored in the data buffer memory for a certain number of words or more. If so, the transfer of data from the data buffer memory to the transfer destination storage means is performed by the transfer destination storage means and buffer. And a transfer control unit and a determination unit that instructs the memory monitoring circuit.

Preferably, in the data transfer control device, the buffer memory monitoring circuit controls a counter for counting the data stored in the data buffer memory and an input / output of the data in the data buffer memory according to an instruction from the judging section. And an input / output control unit that operates.

Preferably, in the data transfer control device, the transfer control means specifies a first address counter for designating the address of the transfer source storage means and the address of the transfer destination storage means. Second address counter and a transfer word number counter for designating the number of data to be transferred, and the determination unit is configured to transfer the first data to the buffer memory from the transfer source storage means each time one data is transferred. The contents of the address counter and the transfer word number counter of 1 are updated, and 1 is transferred from the buffer memory to the transfer destination storage means.
The contents of the second address counter are updated each time data is transferred.

Further, preferably, in the data transfer control device, at least one of the storage means is a dynamic memory.

An image processing multiprocessor having an image processing arithmetic processor, a first storage means subordinate to the image processing arithmetic processor, a host arithmetic processor, and a second storage means subordinate to the host arithmetic processor. In a data transfer control device of a processor system, a first-in first-out type data buffer memory for storing transfer data from a first storage means, a counter for counting data stored in the data buffer memory, and data for one data transfer. A register for storing a predetermined number of data to be stored in the buffer memory, a comparison unit for comparing the contents of the counter with the contents of the register, and an input / output control unit for controlling the input / output of data in the data buffer memory. And a buffer memory monitoring circuit having a Address counter for specifying, an address generator for specifying the address of the second storage means, a data counter for specifying the number of data to be transferred, and data to be transferred after arbitrating the data bus right of each of the storage means. Is output to the first storage means, and whether or not data can be stored in the data buffer memory is determined based on the comparison result of the comparison unit. If the data can be stored, the first If the first storage means and the input / output control section are instructed to store the data in the data buffer memory from the storage means and the data buffer memory stores more than the predetermined number of words, the data buffer Transfer control means having a second storage means and a determination section for instructing the input / output control section to transfer data from the memory to the second storage means.

[0015]

The transfer control means and the data monitoring circuit transfer a fixed number of words of data from the transfer source storage means to the data buffer memory. During this transfer, the transfer destination data bus is open. When a certain number of words of data are stored in the data buffer memory, the certain number of words of data stored in the data buffer memory are transferred to the transfer destination storage means by the transfer control means and the data monitoring circuit. During this transfer, the data bus of the storage means of the transfer source is open. In this way, the storage of a fixed number of words of data in the data buffer memory and the transfer of a fixed number of words of data from the data buffer memory to the transfer destination storage means,
Repeatedly, all transfer data is transferred from the transfer source storage means to the transfer destination storage means.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a schematic configuration diagram of a data transfer control device according to an embodiment of the present invention, which is an example when applied to a multiprocessor system. 2 is an operation flowchart of the example of FIG. In FIG. 1, the DMAC
(Transfer control means) 5 includes address counters 5A and 5B
, The word number counter 5C, the determination unit 5D, and the bus control unit 5
E and 5F. 6 is a FIFO (Firs
t In First Out) data buffer memory, in which data from the memory (storage means) 2 or the memory (storage means) 4 is stored in the buffer memory 6, and the stored data is transferred to the memory 2 or 4. It In addition, 7
Is a FIFO monitoring circuit, and this monitoring circuit 7 includes a counter 7A and an input / output control section 7B. The counter 7A counts the data input / output to / from the buffer memory 6. Further, the control unit 7B controls the operation of the buffer memory 6 according to the instruction from the determination unit 5D.

Next, the operation of the example of FIG. 1 will be described by taking the case of transferring data from the memory 2 to the memory 4 as an example. 1 and 2, the MPU 1 specifies the address of the transfer source (memory 2) in the address counter 5A inside the DMAC 5 and the address of the transfer destination (memory 4) in the address counter 5B. Further, after the MPU 1 specifies the number of data to be transferred to the transfer word number counter 5C, the data transfer is activated. When the DMA transfer is activated, the determination unit 5D of the DMAC 5 can write data to the FIFO buffer memory 6 via the control unit 7B of the FIFO monitoring circuit 7 (data is stored in the FIFO buffer memory 6). Not) or not. If it is writable, the determination unit 5 operates the bus control unit 5E, supplies the bus right request signal BR1 ((A) in FIG. 2) to the MPU 1 at time t0, and starts acquiring the bus right. . Then, in response to this bus right request signal BR1, MP
U1 supplies the bus response signal BA1 ((B) of FIG. 2) to the bus control unit 5B at time t1. As a result, the determination unit 5D detects that the bus right of the memory 2 has been released to the DMAC 5. Then, the determination unit 5D takes out the address, which is the content of the address counter 5A,
The data is output to the memory 2 via the bus control unit 5E. further,
The determination unit 5D outputs a read strobe signal (transfer start signal) to the memory 2 via the bus control unit 5E to start data transfer from the memory 2 to the buffer memory 6 (see FIG. 2). (C), (D)). When one piece of data is transferred from the memory 2 to the buffer memory 6, the judging section 5D updates the contents of the address counter 5A and the contents of the word number counter 5C, and reads the next data. Go. Then, the judging section 5D compares the count number of the counter 7A with the constant word number (the number of words that can be stored in the buffer memory 6), and when the count number of the counter 7A becomes equal to the constant word number, the transfer start signal is negated (invalid). ) Do. Furthermore, the signal BR
1 and BA1 are also negated, the bus of the memory 1 is opened to the MPU1, and the MPU1 is made operable.

From the memory 2 to the FIFO buffer memory 6
When the data transfer to the memory 4 is stopped, the data transfer from the FIFO buffer memory 6 to the memory 4 is started. First, the determination unit 5D supplies the bus right request signal BR2 to the MPU 3 via the bus control unit 5F at time t2 (FIG. 2).
(E)). Then, at time t3, when the bus response signal BA2 is supplied from the MPU 3 to the judgment unit 5D via the bus control unit 5F, the judgment unit 5D detects that the bus right for the memory 2 has been acquired (FIG. 2 (F)). next,
The determination unit 5D supplies the content of the address counter 5B and the data transfer start signal to the memory 4 via the bus control unit 5F, and the buffer memory 6 via the control unit 7B.
The data stored in the memory is transferred to the memory 4 ((G) and (H) in FIG. 2). The determination unit 5D monitors the count number of the counter 7A, and when the count number becomes 0, negates the transfer start signal and the bus right request signal BR2. As a result, the bus of the memory 2 is released. Then, the data transfer from the memory 2 to the buffer memory 6 is started again.

These series of data transfer operations (memory 2 →
(Data transfer from the buffer memory 6, the buffer memory 6 to the memory 4), the content of the data transfer word number counter 5C is 0.
Is repeatedly executed until. However, in the last data transfer, the data stored in the FIFO buffer memory 6 becomes less than the storable data number in the buffer memory 6. In this case, the determination unit 5D
When the remaining word number of the data transfer word number counter 5C becomes 0, the data transfer from the memory 2 to the buffer memory 6 is stopped. This allows the designated data to be accurately transferred.

In the above-described embodiment of the present invention, the time T required for data transfer can be expressed by the following equation (1). T = (tM1 + tM2) × number of data + (tA1 + tA
2) × number of data / buffer memory capacity-(1) where tM1 and tM2 are access times to the memories 2 and 4, and tA1 and tA2 are arbitration times to the memories 2 and 4. Is. From the above equation (1), when the ratio of the number of data to be transferred and the capacity of the buffer memory 6 is small, high speed data transfer similar to the burst mode transfer can be performed. Also, during transfer, DMAC
5 occupies the buses of the memories 2 and 4 only for the time required to transfer data between the transfer source / destination memories 2 and 4 and the buffer memory 6, respectively, and at other times. , MPUs 1 and 3 can access the memories 2 and 4. Therefore, the data processing capacities of the MPUs 1 and 3 are equivalent to those in the cycle still mode transfer.

Further, the transfer source and transfer destination memories 2 and 4 can transfer data asynchronously. Therefore, when a DRAM is used for one of the memories, it is possible to access data to this DRAM at high speed. In other words, general DRAM access is performed by a two-step procedure in which a high-order address (row address) is first specified for the memory and then a low-order address (column address) is switched to. Every time (Simple mode access). In this case, address switching (switching from row address to column address)
It takes time, and it is difficult to improve the access speed to the DRAM. Therefore, of the multiple addresses,
If there is a common row address (within the same page),
Specify the row address once, and for one address,
Performs simple mode access. After that, since the row address is common to the other addresses, only the column address is switched and accessed, so that high-speed access is continuously executed (burst mode access).

In the example of FIG. 1, memory 2 and memory 4
Is accessed asynchronously with. Therefore, when a DRAM is used for the memory 2 or the memory 4, this DR
The burst mode access described above can be executed for AM, and high-speed access can be performed. In this case, if the amount of data to be stored once in the buffer memory 6 is one page of the DRAM, operations such as determination of the DRAM page boundary and resetting of the row address at the page boundary are unnecessary during data transfer. Becomes This facilitates the control of data transfer and improves the transfer speed.

FIG. 3 shows another embodiment of the present invention, which is an example applied to data transfer of a nuclear magnetic resonance imaging apparatus which is a multiprocessor system for image processing. Figure 3
8 is a high-speed image processing arithmetic processor (IP (Image Process Processor) for performing data processing such as image processing arithmetic.
r)), 20 is a memory subordinate to the processor 8 (first
Storage means). Further, 9 is a host arithmetic processor (HP (Host Processer)) for displaying the result of the arithmetic operation performed by the processor 8 and for controlling the entire apparatus, and 40 is
An image memory (second storage means) subordinate to the processor 9, 11 is a display control circuit, and 10 is a display (CRT). The DMAC 50 also includes a bus control unit 54, a data counter 51, an address counter 55, a control register 56, a point register 53, an address generator, and a determination unit 57. Then, the FIFO monitoring circuit 70 includes a register 71, a counter 72, and a comparator 7.
3, an input / output control unit 74 is provided.

The display 10 is assumed to display monochrome 256 gradations with 8 bits (1 byte) / pixel.
The size of the display 10 is 720 × 512 pixels. In the example of FIG. 3, when an image having a size of 256 × 256 pixels is to be displayed on the display device 10, the display data is
Data (image processing calculation result) alone requires 64 kilobytes of data. If the image is processed by the processor 8 and then displayed, for example,
Even if it is a simple 2 × 2 pixel filter calculation process (calculation of the average value of four surrounding points), the number of accesses to the memory 20 is large. That is, the memory 20 is accessed five times in total for reading data of at least 4 points and storing the filter calculation result for each pixel of data.
Will be needed. As a result, when the data of one screen is processed, a total of 64 km × 5 = 320,000 memory accesses are required. Furthermore, when trying to execute complicated image processing (combination of a plurality of filter processing, image enlargement, etc.), the number of accesses to the memory 20 increases several times. Therefore, in order to improve the processing speed of the processor 20, it is necessary to increase the operation speed (clock frequency) of the processor 20 itself and to increase the memory access speed by using a high-speed memory element. I have to. Therefore, in the example of FIG. 3, a high-speed static RAM (SRA) with an access time of 20 nanoseconds is used as the memory 20 for image processing.
M) is used so that one memory access can be performed in 40 nanoseconds in consideration of delay time such as switching time of supply address to the memory 20.

On the other hand, with respect to the memory 40, writing / reading of display data from the memory 20 directly from the processor 9 or via the DMAC 50 and reading of display data from the display control circuit 11 are independently performed. Must be done. In addition, a display device 10 of 720 × 512 pixels
An image memory having a capacity of 360 kilobytes is required to display one screen. Therefore, there is no need to specify a dynamic memory (DRAM (memory can be highly integrated, access time is 100 nanoseconds)) that has a data port that enables memory access by specifying an address. A video RAM in which a serial port capable of reading DRAM data of consecutive addresses is built in one IC in synchronization with a clock of megaHz (40 nanoseconds per cycle) is used. The contents of the image memory 40 are continuously transferred to the display control circuit 11 in synchronization with the one-pixel display clock of the display device 10. Then, the data read from the image memory 40 is converted into the display signal of the display 10 in the display control circuit 11,
It is displayed on the display 10. From the above, in the example of FIG. 3, the display image is changed by rewriting the display data of the image memory from the data port side.

In the DMAC 50, the address of the memory 20 which is the transfer source is designated in the address counter 55 and the two-dimensional coordinates (X, Y) corresponding to the address of the image memory 40 which is the transfer destination are designated in the point register 52. Is specified. The address generator 53 also expands the two-dimensional coordinates into physical addresses in the memory 40.
The bus control unit 54 performs bus arbitration to the memories 20 and 40 and address output. In the data counter 51, the number of pieces of data to be transferred is designated. The control register 56 recognizes the start of transfer and the transfer status. In the FIFO monitoring circuit 70,
In the register 71, the amount of data stored in the buffer memory 6 in one transfer (X size of transferred image) is designated. Further, the counter 72 counts the number of transfer words for each transfer. Then, the comparator 73 compares the content of the register 71 with the content of the counter 72. In addition, FIF
The O buffer memory 6 has a memory capacity of 1 kilobyte so that the data (720 bytes) for one line of the screen at the maximum can be transferred at one time.

FIG. 4 is a detailed configuration example of the example of FIG. With reference to the example of FIG. 4, the data transfer operation when the image data of 256 × 256 pixels is transferred with the left end of the screen of the display device 10 as the origin (coordinates X: 0, Y: 0) will be described. .
The determination unit 57 of the DMAC 50 uses the memory 20 that is the transfer source.
Is set in the address counter 55, and 0 is set in the X and Y parts of the point register 52. Furthermore, the determination unit 57 determines the number of data to be transferred (256 × 256 = 6).
5536) is set in the data counter 51. The determination unit 57 also sets the number of data (256) stored in the buffer memory 6 in one transfer in the X size register 71 of the FIFO monitoring circuit 70. Then, the judgment unit 57 sets activation of data transfer in the control register 56.
The contents set in the address counter 55 are copied to the memory address output counter 542 of the bus control unit 54. The contents set in the point register 52 are
Offset register 531 of address generator 53
And copied to the raster counter 532. Then, the determination unit 57 writes the transfer command in the control register 56.

Next, the judging section 57 supplies a transfer start signal to the bus right requesting section 541 of the bus control section 54. Then,
The bus right request unit 541 supplies the bus request signal IBR for acquiring the bus right to the processor 8 to start arbitration. When recognizing that the bus right may be released, the processor 8 sends the bus response signal IBA to the bus right requesting unit 5
It is supplied to the determination unit 57 via 41. When the bus response signal IBA is supplied, the determination unit 57 starts reading data from the memory 20. First, the content of the memory address output counter 542 is output on the bus as the address of the memory 20. Then, the memory read strobe signal RSTB is supplied from the judging section 57 to the memory 20. In addition, the determination unit 57 controls the buffer memory 6 via the control unit 74, and the buffer memory 6 is changed from the memory 20.
The data transfer to is started. When the reading of one piece of data is completed, the judging section 57 updates the contents of the memory address output counter 542 and subtracts the contents of the data counter 51. Further, the update of the counter 72 of the FIFO monitoring circuit 70 is executed.

The above data read sequence is FI
The operation is repeated until the content of the counter 72 of the FO monitoring circuit 70 matches the content of the X size register 71 (256 times). That is, the contents of the X size register 71 and the contents of the counter 72 are compared by the comparator 73. And
When the contents of the register 71 and the contents of the counter 72 match, the comparator 73 supplies the final DMA signal ILD indicating that the next transfer is final to the determination unit 57. When the signal ILD is supplied, the judging section 57 negates the next read strobe signal RSTB and stops the data transfer. Then, the signal IBR signal is negated and the memory 2
Open the 0 bus. If the content of the data counter 51 becomes 1 before the content of the register 71 and the content of the counter 72 match when the data is transferred from the memory 20 to the FIFO buffer memory 6, the determination unit 57 Signal I
The same operation is performed as when the LD is detected, and the data transfer is stopped.

When the data transfer of the memory 20 is completed, the judgment unit 57 operates the bus right request unit 543 to supply the bus request signal HBR to the processor 9 and the bus response signal H.
Waiting for BA input (bus arbitration). During execution of arbitration, the calculation unit 533 of the address generator 53 in the DMAC 50 calculates the transfer destination address of the image memory 40 based on the following calculation formula. Image memory address = raster counter × 720 + offset register + image memory start address Image memory address obtained by the above formula (in this example, raster counter 532 and offset register 531 are both 0, so the image memory start address)
Is copied to the address counter 534 in the address generator 53 after the end of the bus arbitration, and is output to the bus of the image memory 40 together with the write strobe signal WSTB. This light strobe signal WST
By B, data reading / image memory writing from the FIFO buffer memory 6 is started. Image memory 4
After transferring one piece of data to 0, the judging section 57 updates the address counter 534, and at the same time, the FIFO monitoring circuit 7
The FE signal indicating whether the FIFO buffer memory 6 is empty is checked through 0, and if it is not empty, the next data is transferred. Then, the transfer of the last data is completed,
When the FIFO buffer memory 6 becomes empty, the determination unit 57 negates the signal HBR, releases the bus, and updates the raster counter 532.

The above-described series of transfer operations are used as one sequence, and these processing sequences are repeated until the content of the data counter 51 becomes 0 (256 times in this example). Then, when the transfer of all the data is completed, the transfer end flag is set in the control register 56. The processor 9 recognizes the end of all data transfer by checking this flag.

Based on the above operation, the time required to transfer data of 256 × 256 bytes is executed by the processor 8 or 9 at that time after the bus request signal is supplied to the processor 8 or 9. Assuming that the memory access is completed once during the middle memory access, T = (100 + 40) x 256 x 256 (data transfer) + (100 + 40) x 256 (arbitration) = 9210880 nanoseconds It takes 9.2 milliseconds (the data transfer in the cycle still mode according to the prior art requires about 18 milliseconds because the number of arbitration times is 256 times that of the embodiment of the present invention). Further, the time for monopolizing the bus at the time of transfer is 40 nanoseconds × 256 × 256 on the processor 8 side, which is about 2.6 milliseconds (about 28% of the whole), and 100 nanoseconds × 25 on the processor 9 side.
With 6 × 256, it takes about 6.6 milliseconds (about 72% of the whole). As a result, the efficiency of data processing can be improved especially on the processor 8 side, as compared with the conventional burst mode transfer in which the buses of the processors 8 and 9 are occupied almost 100%.

[0033]

As described above, according to the present invention, in a data transfer control device of a multiprocessor system, a data buffer memory for storing transfer data and the degree of data accumulation in the data buffer memory are monitored and data input is performed. A buffer memory monitoring circuit for controlling the output and an arbitration of the data bus right are instructed to store a fixed number of words of data in the data buffer memory and to instruct the transfer of data to the transfer destination storage means. Transfer control means for The data bus of the transfer destination storage means is opened at the time of data transfer between the transfer source storage means and the buffer memory, and the data bus of the transfer source storage means at the time of data transfer between the buffer memory and the transfer destination storage means. Is released. As a result, it is possible to realize a data transfer control device in which the data transfer speed is improved as compared with the cycle still mode transfer and the data processing capability is improved as compared with the burst mode transfer.

Further, in the data transfer control device of the image processing multiprocessor system having the image processing arithmetic processor, the first storage means, the host arithmetic processor, and the second storage means, from the first storage means Data buffer memory for storing the transfer data of the memory, a buffer memory monitoring circuit, arbitration of the data bus right of each storage means, and a data from the first storage means to the data buffer memory.
And a transfer control unit for instructing the transfer of data from the data buffer memory to the second storage unit. The data bus of the transfer destination of the second storage means is opened at the time of data transfer between the first storage means and the buffer memory, and the data bus of the transfer source storage means at the time of data transfer between the buffer memory and the transfer destination storage means. The data bus is released. As a result, it is possible to realize the data transfer control device of the image processing multiprocessor system in which the data transfer speed is improved as compared with the cycle still mode transfer and the data processing capability is improved as compared with the burst mode transfer.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of an embodiment of the present invention.

2 is a timing chart showing the operation of the example of FIG.

FIG. 3 is a schematic configuration diagram of another embodiment of the present invention.

FIG. 4 is a diagram showing a detailed configuration example of the example of FIG.

FIG. 5 is a schematic configuration diagram of a conventional data transfer control device.

6 is a timing chart showing the operation of the example of FIG.

FIG. 7 is a timing chart showing an operation of burst mode transfer.

FIG. 8 is a timing chart showing an operation of cycle still mode transfer.

[Explanation of symbols]

 1, 3 Microprocessor 2, 4 Memory 5 DMA Controller 5A, 5B Address Counter 5C Word Number Counter 5D Judgment Section 5E, 5F Bus Control Section 6 FIFO Buffer Memory 7, 70 FIFO Monitoring Circuit 7A, 72 Counter 7B, 74 Control Section 8 Image Processor 9 Host Processor 10 Display 11 Display Control Circuit

Claims (5)

[Claims] 1. A data transfer control device for a multiprocessor system having a plurality of microprocessors and storage means subordinate to each of the plurality of microprocessors, wherein first-in first-out data storing the transfer data from the storage means is provided. A buffer memory and a buffer memory monitoring circuit that monitors the degree of data accumulation in the data buffer memory and controls the data input / output of the data buffer memory; When it is detected that the data can be stored in the data buffer memory by the bus control unit which outputs the address of the above to the storage unit and the buffer memory monitoring circuit, the data is transferred from the transfer source storage unit to the data buffer memory. Storage of data, monitoring of transfer source storage means and buffer memory When data is stored in the data buffer memory in a predetermined number of words or more, the data is transferred from the data buffer memory to the transfer destination storage means, and the transfer destination storage means and the buffer memory monitoring circuit are instructed. And a transfer control unit having a determination unit for instructing to the data transfer control device. 2. The data transfer control device according to claim 1, wherein the buffer memory monitoring circuit counts the data stored in the data buffer memory, and the input of the data in the data buffer memory according to an instruction from the judging section. A data transfer control device comprising: an input / output control unit for controlling output. 3. The data transfer control device according to claim 2, wherein the transfer control means specifies a first address counter for specifying an address of the transfer source storage means and an address of the transfer destination storage means. And a transfer word number counter for designating the number of pieces of data to be transferred, and the determination unit is configured to transfer one data from the transfer source storage means to the buffer memory, Data transfer control characterized by updating the contents of the first address counter and the transfer word number counter, and updating the contents of the second address counter every time one data is transferred from the buffer memory to the transfer destination storage means. apparatus. 4. The data transfer control device according to claim 1, claim 2 or claim 3, wherein at least one of the storage means is a dynamic memory. 5. An image processing multiprocessor comprising an image processing arithmetic processor, a first storage means subordinate to the image processing arithmetic processor, a host arithmetic processor, and a second storage means subordinate to the host arithmetic processor. In a data transfer control device of a processor system, a first-in first-out data buffer memory for storing transfer data from a first storage means, a counter for counting data stored in the data buffer memory, and data for one data transfer. A register for storing a predetermined number of data to be stored in the buffer memory, a comparison unit for comparing the contents of the counter with the contents of the register, and an input / output control unit for controlling the input / output of data in the data buffer memory. And a buffer memory monitoring circuit for designating an address of the first storage means. Address counter for specifying the address of the second storage means, a data counter for specifying the number of data to be transferred, and data to be transferred by arbitrating the data bus right of each of the storage means. Is output to the first storage means, and whether or not data can be stored in the data buffer memory is determined based on the comparison result of the comparison unit. If the data can be stored, the first If the first storage means and the input / output control section are instructed to store the data in the data buffer memory from the storage means and the data buffer memory stores more than the predetermined number of words, the data buffer Transfer control means having a second storage means and a determination section for instructing the input / output control section to transfer data from the memory to the second storage means. Data transfer control device.