JPS6352235A - Picture display system - Google Patents

Abstract

PURPOSE:To give no influence to such a process having high priority as a display action, etc., when a frame buffer memory is shared by a display controller and other bus master modules, by providing a controller to a master module to indicate propriety of an access to be given to the frame buffer memory. CONSTITUTION:When a display controller which performs the display of pictures is executing such a process having high priority as a picture display action, etc., an instruction signal showing an executing state of said display action is given to the display controller. At the same time, the accesses given to a frame buffer memory FBM from other bus master modules are inhibited. Then an instruction signal showing that the display controller is executing an action having low priority is given to said controller to permit accesses given to the FBM given from other bus master modules. Thus it is possible to perform arbitration of accesses to the FBM among bus master modules included in a picture display system.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an access arbitration technique for a frame buffer memory of an image display system. It relates to techniques that are effective when applied to

[Prior art]

A bitmap image display system that expresses characters and figures in pixels, stores them in memory as they are, and reads them sequentially to display a free pattern. It includes a frame buffer memory that stores display data in a rewritable manner, a display controller that performs display address control and drawing operations for the frame buffer memory, and a microprocessor that controls the entire system. Examples of documents describing focus map type image display systems include rLSI Handbook JP554 to JP556, published by Ohm Co., Ltd. on November 30, 1980.

By the way, the drawing operation in such a system is performed during the image non-display period, and in order to improve the efficiency of the system, it is necessary to speed up the drawing operation, especially when handling a large amount of data. Therefore, it is possible to provide multiple display controllers exclusively for drawing operations, but the inventors have also developed a system for image processing such as Fourier transform and feature extraction of information stored in the frame buffer memory, and for the main memory and frame buffer memory. In order to enable high-speed data transfer to and from memory, we considered having a microprocessor directly access the frame buffer memory. That is, a system bus to which the microprocessor is connected and a local bus to which the frame buffer memory is connected are connected by a bidirectional buffer circuit, and an address space that can be directly accessed by the microprocessor is set in the frame buffer memory.

[The point at which the invention attempts to solve]

In an image display system in which a display controller that performs image display and drawing, other display controllers dedicated to drawing operations, and a microprocessor share a frame buffer memory, each of the above devices is a bus master module.
Bus arbitration between them is required. The inventors further investigated this point and found that the local bus cycle of the display system is faster than the system bus cycle, and that the display controller that controls display operations is synchronized with the scanning speed of the CRT display device. It is necessary to supply image display data to such a CRT display device based on the priority for the individual bus master module and the request signal it outputs, as in bus arbitration in a typical multi-microprocessor system. It has become clear that if arbitration control is performed each time, bus arbitration cannot be performed in accordance with the memory cycles of the frame buffer memory necessary for normal display operation.

An object of the present invention is to enable communication between display controllers that perform image display and other bus master modules without affecting high-priority operations such as display operations when they share frame buffer memory. An object of the present invention is to provide an image display system capable of arbitrating access to a frame buffer memory.

The above-mentioned and other eleven novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a display controller for displaying images and other bus master modules each share the frame buffer memory in an accessible manner, and notify the occupied state of access to the frame buffer memory according to the priority operation mode of the display controller. An instruction signal is supplied from the display controller, and a controller is provided for instructing the other bus master module to occupy access to the frame buffer memory or not, depending on whether or not there is an access to the frame buffer memory detected by the instruction signal. It consists of

[For production]

According to the above means, when the display controller for displaying an image is executing a high-priority operation such as an image display operation, the instruction signal gives a notification to that effect to the controller, and the other bus master modules Prohibits access to frame buffer memory, and while the display controller is performing lower priority operations.
An instruction signal indicates this to the controller and allows other bus master modules to access the frame buffer memory, thereby allowing the frame buffer memory to be included in the system without affecting high-priority operations such as display operations. This achieves arbitration of accesses to the frame buffer memory between bus master modules.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of an image display system according to the present invention.

In the figure, FBM is a frame buffer memory as a bitmap memory, and is a dynamic RAM in which image display data set in pixel units is stored in a rewritable manner in correspondence with the display image for one frame.
It mainly consists of memory such as (random access memory).

During image display operation, the frame buffer memory FB
The image display data output in parallel from the display data output terminal of M is converted into serial data by the parallel-to-serial conversion circuit P/S, and the timing is adjusted according to the scanning speed of the CRT (cathode ray tube) display DISP. Accordingly, the data is serially supplied to the CRT display DISP.

A data input/output terminal DATA of the frame buffer memory FBM is coupled to a local data bus LDB, and an address signal input terminal ADDR of the frame buffer memory FBM is coupled to a local address bus LAB.

The system data bus SDB and system address bus SAB in the image display system include, but are not particularly limited to, a mask display controller MDC typically shown as a bus master module, a slave display controller 5DC1, and a microprocessor MP.
U are coupled via respective data input/output terminals and address signal input terminals. Although not shown, the system data bus SDR and system address bus SA
A main memory, a dynamic memory access controller, an image scanner, etc. are connected to B.

The mask display controller MDC has its address signal output terminal and data input/output terminal coupled to the local data bus LDB and local address bus LAB. This master display controller MDC
is the only controller in the system that performs display control operations such as address control for supplying the image display data stored in the frame buffer memory FBM to the CRT display DISP. , performs relatively simple drawing operations such as changing the contents of image display data by rewriting the contents of the frame buffer memory FBM, especially primitive data for image display, and also performs refresh operation control for the frame buffer memory FBM and enlarged display. An attribute operation is performed to collectively output control signals for adopting a special screen display mode such as during the image non-display period.

The slave display controller SDC has an address signal output terminal and a data input/output terminal connected to the local data bus LDB and the local address bus LA.
Combined with B. This slave display controller SDC is a controller dedicated to the above-described drawing operation, and is provided to supplement the drawing operation by the master display controller MDC and improve the drawing function of the entire system.

The microprocessor MPU is responsible for controlling the entire image display system, and in this embodiment, it has an address space that allows direct access to the frame buffer memory FBM. As a result, the microprocessor MPU performs image processing such as Fourier transformation and feature extraction of information, which are advanced drawing operations that cannot be performed by the display controllers MDC and 5D-C, as well as main memory (not shown) or image processing (not shown). It also enables high-speed data transfer functions between the image scanner and frame buffer memory.
For this purpose, the system buses SDB and SAB are connected via a data input/output control circuit IOC comprising a bidirectional buffer circuit (not shown).

They are connected to local buses LDB and LAB, respectively.

Note that since the display controllers MDC and SDC and the microprocessor MPU operate asynchronously with each other, data transfer between them is performed by a so-called handshake method.

For example, when the microprocessor MPU sends a command to the mask display controller MDC or initial loads its internal registers, the microprocessor MPU outputs an address signal for selecting the master display controller MDC and selects the master display controller MDC based on the address signal. When the mask display controller MDC receives the chip select signal formed by the mask display controller MDC, an acknowledge signal DTACK md is sent back to the microprocessor MPU, thereby recognizing the necessary data transfer. Similarly to the above, when the microprocessor MPU transfers necessary data to the slave display controller SDC, the acknowledge signal D T
The transfer of data is acknowledged with an ACK s d sent back from the slave display controller SDC to the microprocessor MPU.

In the image display system of this embodiment, as described above, the mask display controller MDC, which is typically shown as a bus master module, the slave display controller 5DC1, and the microprocessor MP
U shares the frame buffer memory FBM.

Next, a configuration for arbitrating access to the frame buffer memory FBM by each bus master module in such a shared state of the frame buffer memory FBM will be described.

The bus controller BCONT arbitrates access to the frame buffer memory FBM by each bus master module. First, the bus controller BCONT determines the access occupancy state to the frame buffer memory FBM according to the priority operation mode of the mask display controller MDC. To inform, the master display controller MDC outputs a busy signal BUSY. Although not particularly limited, the busy signal BUSY is set to an active level (low level) during execution of the priority operation mode in order to notify the bus controller BCONT of this fact.

The priority operation modes of the mask display controller MDC are, although not particularly limited, basically the above display operations excluding drawing operations, refresh operations, and attribute operations; When drawing priority is specified, such as giving priority to Furthermore, in cases where the frame buffer memory comprises static RAM that does not require refresh operations, refresh operations are excluded from the priority mode of operation.

The display controllers MDC and SDC output draw request signals DRREQmd and DRREQsd for accessing the frame buffer memory FBM and requesting a drawing operation to the bus controller BCONT. Such draw request signal D RRE Q m
Although not particularly limited, d and DRREQsd request a drawing operation depending on their low level. When the microprocessor MPU accesses the frame buffer memory FBM to request a drawing operation or a data transfer operation, it outputs an address signal for selecting the data input/output control circuit ■○C, and performs data input/output based on the address signal. Control circuit I
A request signal REQ output from the OC in response to a chip select signal generated inside the OC is supplied to the bus controller BCONT. Note that the request signal REQ is not particularly limited, but its low level is the level that indicates an access request.

Busy signal BUSY, draw request signal DRRE
The bus controller BCONT to which the draw request signal DRREQsd, the draw request signal DRREQsd, and the request signal REQ are supplied, respectively, outputs the halt signal HALTmd.
and HAL T s d to the display controllers MDC and SDC, and outputs an acknowledge signal ACK to the data input/output control circuit ■○C. The above-mentioned halt signals HALTmd and HALTsd cause frame buffer memories FBM to be sent to the respective display controllers MDC and SDC depending on their low level.
Instruct to prohibit access to. Acknowledge signal A
CK controls the data input/output control circuit IOC to a state where data can be input/output by its low level, and
The acknowledge signal DTACKmp generated in the data input control circuit ○C is set to an access permission instruction level such as a low level to permit the microprocessor MPU to access the frame buffer memory FBM. display controller md
Busy signal BUSY, draw request signal DRREQmd, and halt signal HA input and output to C and SDC
L T m d, draw request signal DRREQsd
, and the halt signal HAL T s d, their instruction levels are changed according to the timing according to the memory cycle of the frame buffer memory FBM. Considering the efficiency of the above, each control signal is
It is designed to be advanced by one memory cycle of the frame buffer memory FBM.

Such bus controller BC:ONT sends a busy signal BU
In other words, when SY is set to low level,
When the master display controller MDC executes the priority operation mode such as the display operation described above, regardless of whether the access request to the frame buffer memory FBM is made by the draw request signal DRREQ m d, the draw request signal DRREQsd, or the request signal REQ, The above halt signal HAL T m d,
The halt signal HAL T s d and the acknowledge signal ACK are set to the access prohibition instruction level for the frame buffer memory FBM, and such instructions are advanced by one memory cycle of the frame buffer memory FBM. At this time, master display controller M
The halt signal HAL T m d at the access prohibition instruction level supplied to the DC is ignored by the master display controller MDC, which outputs the low-level busy signal BUSY indicating that the priority operation mode is being executed, and the priority operation mode is not executed. Therefore, when the busy signal BUSY is set to low level, r! IJ's work is based on frame buffer memory F by other bus master modules (slave display controller SDC and microprocessor MPU).
Priority is given to the access request of BM, and the priority operation can be performed according to the memory cycle of the frame buffer memory FBM.

When the busy signal BUSY is set to high level when the master display controller MDC does not execute the priority operation mode, the bus controller BCONT outputs the draw request signal DRREQmd, the draw request signal D RRE Qs d, and the request signal REQ.
The bus master module MDC, 5DC1, or MPU that accepts the request is allowed to access the frame buffer memory FBM.

That is, when the halt signal HALTmd supplied to the master display controller MDC is set to a high level, the master display controller MDC accesses the frame buffer memory FBM and is enabled for drawing operation. When the halt signal HALTsd supplied to the slave display controller SDC is set to high level, the slave display controller SDC accesses the frame buffer memory FBM and is enabled for drawing operation. Also, microprocessor M
When the acknowledge signal DTACKmp supplied to the PU is set to high level, the microprocessor M
The PU accesses the frame buffer memory FBM to enable image processing and data transfer operations.

Next, the operation of the above embodiment will be explained.

First, the priority operation modes in the master display controller MDC are set to display operation, refresh operation,
And the behavior when set to attribute behavior is the second
This will be explained with reference to the time chart shown in the figure.

When the busy signal BUSY is set to a low level for two memory cycles of the frame buffer memory FBM from time tll to t2, the mask display controller MDC performs display operation, refresh operation, and attribute operation at time tl to t3, which is delayed by one cycle. The address signals required for
The signal is supplied to the BM to execute such priority operation.

From time t2 to 1. When the busy signal BUSY is set to a high level for two memory cycles, the master display controller MDC does not execute the priority operation mode from time t2 to t. At □, the master display controller MDC sends a draw request signal D R
RE Q m d is output to the bus controller BCONT, and when the request is accepted, a high-level halt signal HAL T m d is received, so the time tl is one memory cycle later than the times t2 and t3.
From tr to tr, the master display controller M
The DC sequentially supplies address signals required for the drawing operation to the frame buffer memory FBM to execute the drawing operation.

Time t3 when the busy signal BUSY is set to high level
In the master display controller MDC
At the same time, the draw request signal DRREQmd output from the controller is set to high level and the request for drawing operation is withdrawn, and at the same time, the slave display controller SDC outputs the draw request signal DRRE of low level.
Qsd is output to the bus controller BCONT, and when the request is accepted, a high-level halt signal HAL Tsd is received. , the slave display controller SDC supplies address signals required for a drawing operation to the frame buffer memory FBM to execute the drawing operation. At time t, while this slave display controller SDC is making an access request to the bus controller BCONT, the microprocessor MPU outputs an address signal for selecting the data input/output control circuit IOC, and outputs an address signal to select the data input/output control circuit IOC. Request signal RE of access request level (low level) based on chip select signal
Q starts to be supplied to the bus controller BCONT, but until time t7, the slave display controller S
Since the drawing request by DC has been received first, the microprocessor MPU responds to the request signal REQ.
Acknowledge signal sent back to DTACK m
p is assumed to be an intermediate level of access prohibition levels.

At time t6, the draw request signal DRREQ is output from the slave display controller SDC.
At the same time that sd is set to a high level and the drawing operation request is withdrawn, the master display controller MDC outputs a low-level busy signal BUSY to the bus controller BCONT, thereby canceling the access request from the microprocessor MPU. No response is given, and a display operation with a higher degree of urgency is prioritized, and from time t7 to time t, which is one memory cycle later than that, the master display controller MDC sends the address signal necessary for the display operation. The data is supplied to the frame buffer memory FBM for display operation.

When the busy signal BUSY is set to high level from time t7 to t8, the time is delayed by one memory cycle from that time, and from time txa to txa, the mask display controller MDC does not execute the priority operation mode, but during the high level period. , the access request already made by the microprocessor MPU from time 1s is accepted by BCONT, and the halt signal HA is
During the period from time to to t8° when both LTmd and HAL Ts d are set to low level and no priority operation is performed, the microprocessor MPU receives an acknowledgment of the access permission level (low level) output from the bus controller BCONT. Signal DTACK m p
and thereby frame buffer memory FBM
Access and perform image processing.

Note that the address signal required for accessing the frame buffer memory at this time is the address signal whose output starts from time 4, with several bits for forming the chip select signal removed.

Next, the operation when the priority operation mode in the master display controller MDC is set to refresh operation and attribute operation.

This will be explained with reference to the time chart shown in FIG.

When the busy signal BUSY is set to a low level from time to to time t and the master display controller MDC does not execute a priority operation, if no other bus master modules, including that master display controller MDC, request a drawing operation, the bus controller B
By setting the halt signal HAL T m d supplied from CONT to the master display controller MDC to a high level, the mask display controller MDC that declines is allowed to access the frame buffer memory FBM, and the above-mentioned time is reached. From times t to t2, which are delayed by one memory cycle from times t to t, address signals required for the display operation are output to perform the display operation.

When the busy signal BUSY is set to a low level for one memory cycle of the frame buffer memory FBM at time t1, from time t2 to time t, which is delayed by one memory cycle, the master display controller MDC performs a refresh operation as a priority operation mode or Address signals required for attribute operations are sequentially supplied to the frame buffer memory FBM to execute such priority operations.

When the busy signal BUSY is set to a high level for four memory cycles from time t2 to time t, the master display controller MDC does not execute the priority operation mode from time to to t8°, which is one memory cycle later. , from time 2 to time t, the master display controller MDC transmits the low-level draw request signal DRREQmd to the bus controller BCONT.
In order to receive a high-level halt signal HAL T m d when the request is accepted,
At times to to tr, which are one memory cycle later than times t2 to t, the master display controller MDC sequentially supplies address signals required for drawing operations to the frame buffer memory F B M to perform such drawing operations. perform an action.

At time t, the mask display controller M
Draw request signal D RRE output from DC
At the same time that Q m d is set to high level and the drawing operation request is withdrawn, the slave display controller SDC outputs a low level draw request signal DRREQSd to the bus controller BCONT, and the request is accepted. In order to receive the high level halt signal HALTsd, the time to
Time to to t that is one memory cycle later than 1 s
At step 7, the slave display controller SDC supplies an address signal required for the drawing operation to the frame buffer memory FBM and executes the drawing operation. At time t4 while this slave display controller SDC is making an access request to the bus controller B C'ON T, the microprocessor MPU outputs an address signal for selecting the data input/output control circuit IOC, and the internal The request signal REQ at the access request level is started to be supplied to the bus controller BCONT based on the chip select signal formed at time t.
Up to 7, the above slave display controller SDC
Since the drawing request has been accepted first, the acknowledge signal DTACKmp sent back to the microprocessor MPU in response to the request signal REQ is set to an intermediate level of the access prohibition level.

At time t, a draw request signal DRREQ is output from the slave display controller SDC.
At the same time that sd is set to a high level and the drawing operation request is withdrawn, the master display controller MDC outputs a high-level halt signal HAL T.
By receiving md, the access request from the microprocessor MPU is not accepted, and a display operation with a higher degree of urgency is given priority, and from time t7 to t6, which is one memory cycle later than that, the master display The controller MDC performs a display operation by supplying an address signal required for the display operation to the frame buffer memory FBM.

When the halt signals HALTmd and HALTsd are both set to low level from time t7 to t8,
By prohibiting display controllers MDC and SDC from accessing the frame buffer memory FBM, access requests already made by the microprocessor MPU from time t are accepted, and priority operations and display and drawing operations are not performed at time 1. ．． ~t1
During the period of ゜, the microprocessor MPU receives the access permission level (low level) acknowledge signal DTACK m output from the bus controller BCONT.
p, thereby causing the frame buffer memory F
Access the BM and perform image processing.

According to the above embodiment, the following effects can be obtained.

(1) The master display controller MDC is
By informing the bus controller BCONT by the busy signal BUSY when it performs a priority mode of operation, such as a display operation, the slave display controller SDC or other bus master modules, such as the microprocessor MPU, can use the frame buffer memory Access to the FBM is prohibited, and the busy signal BUSY is transmitted to the frame buffer memory FBM.
Since the timing is changed according to the memory cycle of the bus controller BCO,
NT does not individually determine priorities and access requests for individual bus master modules, and
The exclusive right to access the frame buffer memory FBM can be easily arbitrated between bus master modules without special synchronization with the bus cycle when transferring the exclusive right to use the bus.

(2) In particular, if the input/output timing of signals input/output to the display controller, such as the busy signal BUSY, is set in advance of the memory cycles of the frame buffer memory FBM, handshake efficiency can be improved when arbitrating exclusive access rights. can be improved.

(3) From the above effects, frame buffer memory FB
A microprocessor sharing M with the display controllers MDC and SDC can easily access the frame buffer memory FBM directly, significantly improving the efficiency of drawing operations including image processing.

(4) As a result of the above effects, it is possible to simplify the configuration in which the microprocessor MPU can directly access the frame buffer memory FBM.

Although the invention made by the present inventor has been specifically explained above based on examples, the present invention is not limited to the above-mentioned examples, and various changes can be made without departing from the gist thereof.

For example, in the above embodiment, the mask display controller MDC, the slave display controller 5DC
1 and a microprocessor MPU as a bus master module. However, the system is not limited to this, and it is possible to provide a plurality of slave display controllers or employ a direct memory access controller as a bus master module. You may. Furthermore, in the above embodiment, requests for drawing operations by display controllers are made based on draw request signals, but this is not limited to this, and if the drawing loads of each display controller are approximately equal, , the drawing operation can also be performed in a time-sharing manner by sequentially setting the halt signals supplied to each of them to the access permission level in a predetermined order.

When multiple display controllers or MPUs request non-priority operations at the same time, which device should be granted access permission preferentially is a system-specific problem, and an external path controller determines it. In this example,
Although it is explained that the MPU access has the lowest priority, it is usually better to give the MPU access the highest priority during non-priority operations. Because, M.P.
This is because if U is kept waiting for a long time, system performance will deteriorate.

The priority operation mode of the mask display controller in the above embodiment is not limited to the combination of display operation, refresh operation, and attribute operation, and can appropriately set operations with a high degree of urgency in the image display system.

In the above description, the invention made by the present inventor was mainly applied to a CRT image display system that includes a display controller and a microprocessor as a bus master module, which is the field of application in which the invention was made by the present inventor. The present invention is not limited to this, and can be applied to various image processing systems such as other graphic systems. The present invention is applicable to conditions where at least a plurality of bus master modules share a frame buffer memory.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In other words, a display controller that displays an image and other bus master modules each share a frame buffer memory in an accessible manner, and an instruction signal is sent to inform them of exclusive access to the frame buffer memory according to the priority operation mode of the display controller. is supplied from the display controller, and is provided with a controller that instructs the other bus master modules as to whether or not to access the frame buffer memory, depending on whether or not access to the frame buffer memory is occupied by the instruction signal. , while a display controller that performs image display is executing a high-priority operation such as an image display operation, the instruction signal notifies the controller to that effect and prohibits other bus master modules from accessing the frame buffer memory. This makes it possible to easily arbitrate the state of access to the frame buffer memory between bus master modules included in the system without affecting high priority operations such as display operations.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the image display system according to the present invention, and FIG. 2 shows the operation when the priority operation mode in the mask display controller is set to display operation, refresh operation, and attribute operation. FIG. 3 is a time chart for explaining the operation when the priority operation mode in the mask display controller is set to refresh operation and attribute operation. MDC...Master display controller, SDC
...Slave display controller, MPU...
・Microprocessor, FBM...Frame buffer memory, IOC...Data input/output control circuit, BCO
NT...bus controller, BUSY...busy signal, HALTmd and HALTsd-halt signal, REQ...request signal, ACK and D
TACK mp...Acknowledge signal.・−＼

Claims (1)

[Claims] 1. An image display system in which a display controller for displaying images and another bus master module are connected to each other so that they can access a frame buffer memory, wherein the priority operation of the display controller is Depending on the mode, an instruction signal is output from the display controller to notify the occupied state of access to the frame buffer memory, and depending on whether or not the instruction signal occupies access to the frame buffer memory, the other bus master modules mentioned above An image display system comprising: a controller that instructs access to a frame buffer memory. 2. When the instruction signal indicates an occupied access state of the frame buffer memory during an image display operation and a refresh operation for the frame buffer memory by the display controller, the controller instructs other bus master modules to access the frame buffer memory. 2. The image display system according to claim 1, wherein access to the frame buffer memory by other bus master modules is permitted during a drawing operation period by the display controller.