JPH11282693A - Mcu simulation device, its simulation method and computer redable recording medium recording simulation program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to reduce labor for compiling/linking even when many derived micro central units(MCUs) should be prepared. SOLUTION: The MCU simulation device includes an input means 100 for inputting a program to be debugged and respective instructions, a mapping information generation means 210 for generating the description of processing depending upon a specific address from a source program as mapping information, a compiling/linking means 220 for compiling and/or linking respective simulation parts by description independent of the specific address in the source program, a simulation means 230 for generating access information describing an access between respective simulation parts and executing simulation, and an output means 300 for outputting a simulation result.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a simulation device for a microcomputer for embedded software development, and more particularly to an MCU (micro central unit) simulation device capable of simulating a peripheral input / output device, and a simulation method therefor. And a computer-readable recording medium storing the simulation program.

[0002]

2. Description of the Related Art First, an example of a system configuration in a real embedded system to be simulated is shown in FIG. An MCU (micro central unit) in this system includes a CPU for executing an input target program and a CP for inputting signals from hardware.
It comprises input / output devices a, b, and c for converting an input signal to the U or an output signal from the CPU to an output signal for controlling hardware.

An instruction from the CPU to the peripheral input / output devices a, b, and c is generally given by a read / write instruction to an I / O register provided in each of the input / output devices a, b, and c. Each I / O register is a part of an accessible memory when viewed from the CPU.

In the development of a target program for controlling such an embedded system, it is necessary to verify the control of the peripheral input / output devices together. Therefore, it is necessary to faithfully simulate the MCU including the peripheral input / output devices. There is a need for an MCU simulation device that can perform the above. In order to realize such an MCU simulation apparatus, the MCU includes a CPU and input / output devices a, b, and c.
In the conventional MCU simulation device, the CPU simulation unit that simulates the CPU and the I / O simulation unit a that simulates the input / output devices a, b, and c.
It is realized by being constituted by b, c, and the like.

[0005]

However, in the conventional MCU simulation apparatus as described above, the MC
Since a process depending on a specific address is embedded in a source program for compiling each simulation unit of the U simulation device, a CPU simulation unit for simulating a CPU, another bus simulation unit, an I / O simulation unit, and the like are used. All simulation sections were fixedly linked.

A case where N derived MCUs must be simulated in such a conventional MCU simulation apparatus will be described with reference to FIG.

To simulate an MCU, a source program for compiling and linking each simulation unit of the MCU simulation device is required. If there is a description depending on a specific address in this source program, the description must be updated for each derived MCU using an editor or the like. And
By compiling / linking the updated source programs 01, 02, and 03, the respective MCU simulation apparatuses 01, 02, and 03 are generated.

As described above, in the conventional simulation device in which the respective simulation units are fixedly linked, N
If there are N derived MCUs, N updates of the source program and N compiles / links give
N derivative MCU simulation devices had to be prepared.

In an embedded system, since there are peripheral input / output devices suitable for each of externally connected hardware, there are many MCUs having various input / output devices even if the CPU core is the same. In many cases, only the addresses assigned to the I / O registers are different even in the same device configuration. Therefore, if there is a description depending on a specific address in the source program, it is necessary to update the source program N times and compile / link N times.

In this case, updating the source program does not take much time, but compiling / linking the source program takes a lot of time. Therefore, it is necessary to prepare N derivative MCU simulation apparatuses using a conventional simulation apparatus. If not, it was a big problem.

When a new CPU comes out,
It is necessary to rewrite the program relating to the CPU among the source programs and update and compile / link the source program again as shown in FIG. In this way, not only the program related to the changed CPU, but also the program related to the input / output device,
Since updating and compiling / linking have to be performed again, useless processing has been performed.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an MCU simulation apparatus which does not need to compile / link N times even when many derived MCU simulation apparatuses must be prepared. And a computer-readable recording medium storing the simulation method and the simulation program.

[0013]

In order to achieve the above object, an MCU simulation apparatus according to a first aspect of the present invention has
A CPU simulation unit for simulating the operation of the PU, an I / O simulation unit having I / O registration information for simulating a peripheral input / output device of the CPU, a memory simulation unit having memory registration information for simulating a memory, and An MCU simulation device for simulating an MCU by a bus simulation unit for controlling access between simulation units, comprising: input means for inputting a debugged program to be simulated and a source program; Mapping information generating means for generating, as mapping information, a description of a process depending on a specific address from the source program, and specifying the description from the source program input by the input means. Compile / link means for compiling and linking the CPU simulation section, the I / O simulation section, and the memory simulation section separately, and compiling and linking are performed by the compiling / linking section. The CPU simulation unit, the I / O simulation unit, the memory simulation unit, and the bus simulation unit.
Simulation means for generating access information describing access between simulation units from the mapping information, the I / O registration information, and the memory registration information, and performing a simulation based on the access information; and a simulation result of the simulation means And output means for outputting

According to the first aspect, even when a plurality of MCUs having various input / output devices are simulated, only the I / O simulation units corresponding to the respective input / output devices are dynamically linked. Multiple MCUs
Simulation can be performed.

Another effect of the MCU simulation apparatus of the present invention is that even when a new CPU comes out, if the peripheral input / output device is the same, only the CPU is compiled / linked with the new CPU source program. By doing so, it is possible to simulate the MCU including the new CPU.

According to a second aspect of the present invention, there is provided an MCU simulation method which simulates the operation of a CPU.
An I / O simulation unit having a simulation unit and I / O registration information for simulating a peripheral input / output device of a CPU, a memory simulation unit having memory registration information for simulating a memory, and access control between the simulation units M that simulates an MCU using a bus simulation unit that performs
A CU simulation method, comprising: a mapping information generating step of generating, as mapping information, a description of a process dependent on a specific address from a source program; and a CPU simulation unit for a process independent of a specific address from the source program. A compiling / linking step of separately compiling and linking the I / O simulation section and the memory simulation section; and interpolating between the simulation sections based on the mapping information, the I / O registration information, and the memory registration information. Generating access information describing access, and performing a simulation using each of the simulation units based on the access information.

According to the second aspect of the present invention, it is possible to realize an MCU simulation method having the same effect as that of the first aspect of the present invention.

According to a third aspect of the present invention, there is provided a computer-readable recording medium on which an MCU simulation program is recorded.
An I / O simulation unit having a simulation unit and I / O registration information for simulating a peripheral input / output device of a CPU, a memory simulation unit having memory registration information for simulating a memory, and access control between the simulation units M that simulates an MCU using a bus simulation unit that performs
A computer-readable recording medium on which a simulation program of a CU is recorded, wherein a mapping information generation process for generating a description of a process dependent on a specific address from a source program as mapping information, Compile / link processing for compiling and linking each of the CPU simulation section, the I / O simulation section, and the memory simulation section separately;
A simulation process of generating access information describing access between the simulation units from the O registration information and the memory registration information, and performing a simulation using the simulation units based on the access information. It is characterized by being executed by a computer.

According to the third aspect, it is possible to realize a computer-readable recording medium on which an MCU simulation program having the same effect as that of the first aspect is recorded.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of an MCU simulation apparatus, a simulation method thereof, and a computer-readable recording medium storing the simulation program according to the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an MCU simulation apparatus according to the present invention.

As shown in FIG. 1, the MCU simulation apparatus according to the present invention depends on an input means 100 for inputting a debugged program or a source program to be simulated, each instruction, etc., and a specific address from the source program. Mapping information generating means 210 for generating a description of a process as mapping information
And a compiling / linking means 220 for compiling and linking according to a description of processing independent of a specific address from a source program, a CPU simulation section, an I / O simulation section, a memory simulation section, and a bus simulation section. Simulation means 230 for generating access information describing access between simulation units from mapping information, I / O registration information, and memory registration information, and performing a simulation based on the access information; and output means for outputting a simulation result. 300.

Here, the simulation means 230
As shown in FIG. 2, a CPU simulation unit 231 including a virtual register 101 and a virtual I / O register 102
And an I / O simulation unit 232 including the I / O register registration information 103 having registration information on each virtual I / O register 102, and a memory registration information 105 having registration information on each virtual memory 104 and each virtual memory. It comprises a memory simulation unit 233 and a bus simulation unit 234 including the access information 106.

The input means 100 includes a keyboard, a mouse, a light pen, a flexible disk device and the like, and the processing means 200 has a C for performing various processes.
A conventional computer system including a PU and storage means for storing instructions for this processing is included.
00 includes a display device, a printer device, and the like. Instructions and timing constraints for the respective processes of the mapping information generating means 210, the compiling / linking means 220, and the simulation means 230 included in the processing means 200 are stored in the storage means, and are loaded into the CPU as necessary and executed. Done. Usually, control of execution is
This is performed by an operator inputting a command (command) to the input unit 100.

Next, the operation of the MCU simulation apparatus of the present invention will be described, and the MCU simulation method of the present invention will also be described.

First, a program to be debugged DP, a source program SP, and each instruction are input to the input means 100.
The debugged program DP is a program to be debugged.

When each program or each instruction is input to the input unit 100, the mapping information generating unit 210 generates a description of a process depending on a specific address from the description of the source program SP as mapping information MI. This mapping information MI is information provided to the bus simulation unit 234 to allocate the virtual I / O register 102 to an arbitrary address of the target memory. As shown in FIG. 3, the content of the mapping information MI is composed of a start address, a data length, and a unique ID for identifying the register for each virtual I / O register. The ID does not matter whether it is a number or a register name. The mapping information MI is prepared according to the configuration of the peripheral input / output device of the target MCU to be simulated.

Next, when the mapping information MI is generated, the compiling / linking means 220 compiles and links each simulation unit of the simulation means 230.

In the compiling and linking, from the description of the source program, another source program for each CPU and each peripheral input / output device, that is, a CPU source program and an I / O source program are prepared, and the CPU and each peripheral input / output device are prepared. Compile and link each I / O device.
At this time, since the processing depending on the specific address is described in the mapping information MI,
The source program or the like contains only a description of a process that does not depend on a specific address.

FIG. 4 shows a program module configuration according to the present invention.

When simulating the MCU simulation device 01, first, the CPU source program a compiles / compiles the CPU simulation unit a.
Link, and I / O source programs a, b,
I / O simulation units a, b, c, d by c and d
Is compiled / linked. Since each source program does not include a process depending on a specific address in the program, MC having various types of input / output devices is used.
When simulating U respectively, each I / O for simulating the peripheral input / output devices a, b, c, d
By simply dynamically linking the O simulation units a, b, c, and d with the CPU simulation unit, an MCU simulation apparatus that simulates each MCU can be created. For example, when simulating the MCU 01 including the input / output devices a and b, the CPU simulating the MCU 01 is performed by dynamically linking the CPU simulation unit a and the I / O simulation units a and b during the simulation.
The U simulation device 01 can be created, and when simulating the MCU 02 including the input / output devices a, b, and c, the CPU simulation unit a and the I / O simulation units a, b, c
The MCU simulation device 02 that simulates the MCU 02 can be created by dynamically linking.

FIG. 5 shows an image of the MCU simulation apparatus of the present invention. Before execution, the MCU simulation apparatus 50 having the I / O simulation units a, b, and c
There is one. Since the MCU simulation apparatus 501 is in a state before execution, the I / O register of each I / O simulation unit is not allocated to an address of the bus simulation unit.

When derivative products A, B, and C are generated from the MCU simulation device 501, the I / O registers A, B,.
, I are generated by allocating I to each address of the bus simulation unit with reference to the mapping information A, B, C.

The peripheral input / output device has an I / O register for designating a mode and a parameter for controlling the operation for each device, and is usually assigned to an arbitrary address on the MCU.
It operates by reading / writing data to or from the arbitrary address.

According to the present invention, mapping information A, B, and C are prepared in which address information to be allocated to the I / O registers is prepared in consideration of the address configuration of the I / O registers of the target system to be simulated. Specify the device. A virtual I / O register can be assigned to an arbitrary address based on the specified mapping information.
C can be constructed respectively. Therefore, a plurality of Ms having different configurations of peripheral input / output devices can be executed by one execution module.
Simulation of a CU can be realized.

Another effect of the MCU simulation apparatus of this embodiment is that even when a new CPU comes out, if the peripheral input / output devices are the same, only the CPU is compiled / linked with the new CPU source program. By doing so, a simulation can be performed.

For example, as shown in FIG.
b, the CPU source program b is prepared, compiled / linked, and dynamically linked using the existing peripheral input / output devices b, c, d.
It is possible to realize the MCU simulation device 03 that performs the simulation of the third embodiment. Conventionally, processing dependent on a specific address was included in the source program, so if the CPU or one of the peripheral input / output devices changed,
Although the entire source program has to be rewritten, in the present application, only the CPU source program needs to be rewritten, so that the labor required for the simulation is greatly reduced.

Next, when the compiling and linking of each simulation unit by the compiling and linking means 220 is completed, the simulation by the simulation means 230 is performed. In the simulation means 230, two processes of a mapping process sequence and an instruction execution process sequence are performed.

First, the processing of the mapping processing sequence will be described with reference to the flowchart shown in FIG. In this mapping processing sequence, the access information 106 is generated from the I / O register registration information 103, the memory registration information 105, and the mapping information MI.

First, as shown in FIG. 6, the I / O register registration information 103 is obtained from the I / O simulation unit 232 (S601). This I / O register registration information 10
3 is registered when the I / O simulation unit 232 is initialized.

The contents of the I / O register registration information are shown in FIG.
As shown in the figure, a unique I
D, the address of the read event processing unit, and the address of the write event processing unit.

Here, the event processing unit is a virtual I / O
Refers to the first address on the host machine where the processing to be executed at the time of reading and writing to the register is described. The read event processing section address is the address of the event processing routine to be processed at the time of reading the I / O register. And the write event processing unit address is I
This is the address of the event processing routine to be processed when writing to the / O register.

Next, the memory registration information 105 is obtained from the memory simulation unit 233 (S602). This memory registration information 105 is stored in the memory simulation unit 23.
3 is initialized when it is initialized, and its contents are the same as the I / O register registration information in FIG.

Next, the mapping information MI generated by the mapping information generating means 210 is obtained (S603).
Then, the access information 106 is generated as shown in FIG. 8 by associating the ID described in the acquired I / O register registration information 103 or the memory registration information 105 with the ID of the mapping information MI (S604).

The access information 106 represents information of a read event processing unit or a write event processing unit for an arbitrary address.

When the access information 106 is created and the CPU simulation unit 231 accesses an arbitrary virtual I / O register 102 or virtual memory 104, the access information 10
6 can be accessed. As shown in FIG. 8, the access information includes an address, a data length, a read event processing unit address, and a write event processing unit address. However, in the present embodiment, one access information corresponding to one address is assigned, but the configuration of the access information is not particularly limited as long as the address of the event processing unit to be called can be specified by the address. And

In the flowchart of FIG. 6, the I / O register registration information 103, the memory registration information 105, and the mapping information MI are obtained in this order, but this order can be arbitrarily changed.

Next, the instruction execution processing sequence will be described with reference to the flowcharts of FIGS. 9, 10, 11, and 12.

First, according to the flowchart of FIG.
The processing in the U simulation unit 231 is started. C
The PU simulation unit 231 decodes the program to be debugged DP and virtually executes the instruction code. That is, it is for simulating the operation of the CPU of the target system.

In FIG. 9, when the program to be debugged DP inputted by the input means 100 is loaded and the program execution processing sequence is started, first, preparation before instruction execution S901 is performed. This instruction pre-execution preparation S90
In step 1, the instruction code of the target program is replaced with a virtual instruction on the host machine. That is, one instruction to be simulated is replaced with a plurality of virtual instructions. Then, a virtual instruction to be executed is extracted from the plurality of replaced virtual instructions (S902). From this step S902, execution of the processing routine of the replaced virtual instruction is started. Some virtual instructions generate a bus access and some do not. Therefore, it is determined whether or not the extracted virtual instruction causes a bus access to the memory or the I / O register (S903). If no bus access occurs, execution of virtual instruction S
If the processing of step 904 is performed and a bus access occurs, preprocessing S905 for bus operation is performed.

The execution of the virtual instruction performed in step S904 when no bus access occurs means access to the virtual register 101 and various flags in the CPU simulation unit 231 accompanying various operations and storage of the operation results. I do. When the execution is completed, step S9 is performed.
In step S906, if there is no virtual instruction, it is determined that one instruction to be simulated has been completed, and the execution of the instruction is terminated. If there is a virtual instruction, the flow returns to step S902, and the above processing is performed. repeat.

If a bus access occurs in step S903, the data is passed to the bus simulation unit 234 in step S905. There are two types of data to be passed, one is the address of the access destination, the other is the data to be written in the case of a write operation, and the address for storing the data to be read in the case of a read operation. .

When the data is transferred, step S907
The bus operation occurs, and the CPU simulation unit 231 makes an access request to the bus simulation unit 234. Here, the execution is performed from the CPU simulation unit 231 to the bus simulation unit 23.
It will move to 4.

Next, the processing of the bus simulation unit 234 will be described with reference to the flowchart of FIG.

The bus simulation unit 234 has a CPU
It performs execution control, scheduling, and access control between the simulation unit 231, the I / O simulation unit 232, and the memory simulation unit 233. All accesses from the CPU simulation unit 231 to any memory or I / O register are performed in the bus simulation unit 234 with reference to the access information 106.

First, when the bus operation is started in FIG. 10, the data passed in step S905 in FIG. 9 is received from the CPU simulation unit 231 (S
1001). The access destination address is extracted from the received data (S1002), and step S1 is executed.
The process proceeds to the acquisition process of the event processing unit of 003.

FIG. 11 shows the process of obtaining the event processing unit.
A description will be given based on the flowchart of FIG.

First, the address of the access destination extracted in step S1002 is received (S1101). The event processing unit is specified from the access destination address and the access information 106 (S1102). The specified event processing unit is returned to the caller (S1103), and the process returns to the bus operation flowchart of FIG. 10 and proceeds to step S1004.

In step S1004, the data to be written is passed to the execution of the event processing unit in the case of a write operation, and the storage address of the data to be read is passed in the case of a read operation.
To the execution of the event processing unit.

The execution is performed by the bus simulation unit 2
From 34, the processing moves to the I / O simulation section 232 or the memory simulation section 233. Access destination is I / O
When it is the simulation unit 232, the process proceeds to the I / O simulation unit 232, and when it is the memory simulation unit 233, the memory simulation unit 233
Execution moves to Here, the case where the execution shifts to the I / O simulation unit 232 will be described, but the same processing is performed when the execution shifts to the memory simulation unit 233.

The I / O simulation unit 232 has a CP
This is for simulating the input / output devices in the vicinity of the U, and not only for the peripheral input / output devices on the one-chip microcomputer but also for the simulation of the external circuit connected to the peripheral input / output devices. The I / O simulation unit 232 includes the virtual I / O register 102 and the I / O register registration information 103.
It operates based on the set value of the register 102.

The virtual I / O register 102 corresponds to an I / O register of a peripheral input / output device, holds an operation mode and parameters of the I / O simulation unit 232, and operates the I / O simulation unit 232. Is determined.

In the I / O register registration information 103, information corresponding to each virtual I / O register 102 is registered, and is registered at the time of system initialization or the like.

In order to correctly allocate the virtual I / O register 102 on the memory, the ID of the mapping information MI and the I
The ID of the / O register registration information 102 must match. The I / O register registration information 103 is M
It does not depend on the peripheral circuit configuration of the CU.

The memory simulation unit 233
Is for simulating a memory, holds a program to be debugged DP, and includes memory registration information 105 to the bus simulation unit 234. Then, registration is performed at the time of system initialization or the like. The contents of the memory registration information 105 are the same as the I / O register registration information 103.

Here, the execution process of the event processing unit is shown in FIG.
This will be described with reference to the flowchart of FIG.

First, the storage destination address of the write data or read data passed in step S1004 is received from the caller (S1201). Then, the received data is transferred to the virtual I / O register 102 or the virtual memory 1.
A simulation of an input / output operation such as writing to the file 04 is performed (S1202).

Next, in the case of a read operation, the data is stored in the storage destination address of the received data, so that the calling bus simulation unit 23
4 is returned to S4 (S1203). The data to be stored is mainly the values of the virtual I / O register and various flags. In the case of a write operation, no data is returned.

Here, returning to the bus operation flowchart of FIG. 10, the process proceeds to step S1006. In step S1006, in the case of a read operation, data is returned to the CPU simulation unit 231 of the calling source. The returned data is the data returned during the execution processing (S1005) of the event processing unit.
The method of returning data is performed by storing the return data in step S1005 for the storage address of the data to be read.

Here, returning to the flowchart of FIG. 9, the process proceeds to step S906.

In step S 906, if a virtual instruction exists, the process returns to step S 902 to repeat the above-described processing. If no virtual instruction exists, it is determined that one instruction to be simulated has ended, and the instruction execution processing ends. .
And when all the instructions have been simulated,
The result of this simulation is output from the output means 300.

FIG. 13 shows the above-described instruction execution processing sequence in a time series. FIG. 13 shows a time-series data transfer relationship between the simulation units when executing the instruction execution processing sequence in the simulation means 230. Time elapses below the vertical axis.

First, the simulation is started by the CPU simulation unit 231 and when a bus access occurs in step S903, the CPU simulation unit 23
The execution moves from 1 to the bus simulation unit 234. Then, the address of the access destination is taken out (S1002),
After performing processing such as acquisition of the event processing unit (S1003), execution shifts from the bus simulation unit 234 to the I / O simulation unit 232 in the execution processing of the event processing unit (S1005). After the input / output operation (S1202) is performed in the I / O simulation unit 232, the data is returned to the bus simulation unit 234 (S1203), and the execution returns from the I / O simulation unit 232 to the bus simulation unit 234. further,
The data is returned to the CPU simulation unit 231 (S1006), and the bus simulation unit 234
Execution returns to the PU simulation unit 231.

As described above, data transfer is performed between the simulation units when executing the instruction execution processing sequence.

A program for realizing the above-described MCU simulation method can be stored in a recording medium. By reading this recording medium by a computer system, the program is executed while controlling the computer. The above-described MCU simulation method can be realized. Here, the recording medium includes a device capable of recording a program, such as a memory device, a magnetic disk device, and an optical disk device.

[0076]

As described above, in the MCU simulation apparatus of the present invention, among the descriptions of the source program, the description relating to the processing depending on a specific address is described in the mapping information MI, and does not depend on the specific address. The description about the processing is described in the CPU source program and the I / O source program prepared by the compiling / linking means, so that even when simulating a plurality of MCUs having various input / output devices, each input / output device can be simulated. I corresponding to the output device
Simulating a plurality of MCUs can be performed only by dynamically linking the / O simulation units.

Another effect of the MCU simulation apparatus of the present invention is that even when a new CPU comes out, if the peripheral input / output devices are the same, only the CPU is compiled / linked with the new CPU source program. As a result, the simulation of the MCU including the new CPU can be performed, so that the useless processing is significantly reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of an MCU simulation apparatus according to the present invention.

FIG. 2 is a block diagram showing a configuration of an embodiment of a simulation unit of the MCU simulation apparatus of FIG. 1;

FIG. 3 is a diagram illustrating an example of the content of mapping information.

FIG. 4 is a diagram showing a program module configuration of the MCU simulation device of the present invention.

FIG. 5 is a diagram showing an image of an MCU simulation device of the present invention.

FIG. 6 is a flowchart showing a mapping processing sequence in the MCU simulation apparatus according to the present invention.

FIG. 7 is a diagram illustrating an example of the contents of I / O register registration information and memory registration information.

FIG. 8 is a diagram illustrating an example of the content of access information.

FIG. 9 is a flowchart showing an instruction execution processing sequence in the MCU simulation apparatus according to the present invention.

FIG. 10 is a flowchart showing a bus operation in the flowchart of FIG. 9;

11 is a flowchart showing an acquisition process of the event processing unit in the flowchart of FIG.

FIG. 12 is a flowchart showing an execution process of an event processing unit in the flowchart of FIG. 10;

FIG. 13 is a diagram showing, in chronological order, an instruction execution processing sequence in the MCU simulation apparatus according to the present invention.

FIG. 14 is a block diagram illustrating a system configuration example of a real embedded system to be simulated;

FIG. 15 is a diagram showing a program module configuration of a conventional MCU simulation apparatus.

DESCRIPTION OF SYMBOLS 100 input means 101 virtual register 102 virtual I / O register 103 I / O register registration information 104 virtual memory 105 memory registration information 106 access information 200 processing means 210 mapping information generating means 220 compiling / linking means 230 simulation means 231 CPU simulation section 232 I / O simulation section 233 Memory simulation section 234 Bus simulation section 300 Output means

Claims (3)

[Claims] 1. C for simulating the operation of a CPU
CPU having PU simulation unit and I / O registration information
MCU simulation is performed by an I / O simulation unit that simulates a peripheral input / output device, a memory simulation unit that has memory registration information and simulates a memory, and a bus simulation unit that performs access control between the simulation units. An MCU simulation apparatus, comprising: input means for inputting a debugged program to be simulated and a source program; and a description of processing depending on a specific address from the source program input by the input means as mapping information. A mapping information generating unit for generating, and a process which does not depend on a specific address from the source program input by the input unit.
Compile / link means for separately compiling and linking the U simulation section, the I / O simulation section, and the memory simulation section; and the CPU simulation section and the I / O section compiled and linked by the compile / link means. /
An O simulation unit, the memory simulation unit, and the bus simulation unit, and generate access information describing access between simulation units from the mapping information, the I / O registration information, and the memory registration information. A simulation means for performing a simulation based on the access information; and an output means for outputting a result of the simulation performed by the simulation means. 2. C for simulating the operation of the CPU
CPU having PU simulation unit and I / O registration information
An I / O simulation unit for simulating peripheral input / output devices, a memory simulation unit having memory registration information and simulating a memory, and a bus simulation unit for controlling access between the simulation units are used for the MCU. A method of simulating an MCU for performing a simulation, comprising: a mapping information generating step of generating a description of a process dependent on a specific address from a source program as mapping information; and a process independent of a specific address from the source program. CPU simulation unit, I
A compiling / linking step of separately compiling and linking the / O simulation unit and the memory simulation unit; and describing an access between the simulation units based on the mapping information, the I / O registration information, and the memory registration information. A simulation step of generating access information to be performed and performing a simulation using each of the simulation units based on the access information. 3. C for simulating the operation of the CPU
CPU having PU simulation unit and I / O registration information
An I / O simulation unit for simulating peripheral input / output devices, a memory simulation unit having memory registration information and simulating a memory, and a bus simulation unit for controlling access between the simulation units are used for the MCU. A computer-readable recording medium on which a simulation program of an MCU to be simulated is recorded, wherein: a mapping information generation process for generating a description of a process depending on a specific address from a source program as mapping information; The CPU simulation unit performs the processing independent of the address of
A compile / link process for separately compiling and linking the I / O simulation unit and the memory simulation unit; and describing access between the simulation units based on the mapping information, the I / O registration information, and the memory registration information. Generating access information to perform the simulation using the respective simulation units based on the access information, and causing the computer to execute these processes.
A computer-readable recording medium recording a CU simulation program.