JP3270729B2 - Extended instruction set simulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a simulation of an assembler language used in information processing and a simulation of a function model of peripheral hardware in an embedded system.

[0002]

2. Description of the Related Art In debugging of software for checking whether a program written in an assembler description or a machine language of a target computer is correct, in debugging of software for checking whether operation on a target computer is correct or not. 2. Description of the Related Art There is known an instruction set simulator that sequentially interprets and simulates each of the assembler instructions (one instruction in a machine language) using a computer different from the computer. FIG.
FIG. 1 is a diagram showing a basic configuration of a first conventional instruction set simulator. In the figure, 11 is an instruction execution unit of an instruction set simulator, 12 is a data memory, 13 is a register, 14 is an instruction execution unit, 15 is a program counter, 16 is a program (machine language) storage unit, and 17 is a command control unit. 1a is a fetch of one instruction, and 1b is a program address. The user's program (assembler or machine language) is stored in the program memory 16 and an instruction indicated by the program counter PC indicating the address of the memory of the program to be currently executed by the program is fetched. Execution (simulation) is performed. As a result, the values of the memory and the register are updated, and the value of the PC to be executed next is set. By repeating this, the simulation of the program is executed. At this time, the user can appropriately suspend the simulation from the command control unit and observe the state of the memory and the state of the register at that time. This is the basic function of the instruction set simulator.

A second prior art is disclosed in Japanese Patent Application Laid-Open No. 63-2715.
There is one disclosed in Japanese Patent Publication No. 44-44. In this method, when a connection target such as an external storage device and a line is included in a simulation target in addition to a target instruction of a target computer, a non-target instruction is prepared as a user-defined instruction at an assembler level. The simulation is performed by providing means for identifying the user-defined instruction and means for simulating the user-defined instruction. FIG. 7 is a diagram showing the concept of the operation described in the simulation method. In this method, a program for simulation is described in a mixed manner at an assembler level, and the program is read out in step S101 of the figure (hereinafter step description is omitted) for this program, and S10
It is checked whether the instruction is a target instruction originally provided by the simulator, and the target instruction is executed in S103 or a user-defined instruction is executed in S105.

[0004]

Since the conventional simulator is configured as described above, in the first conventional example,
A system consisting only of a microprocessor and a program can perform a simulation sufficiently, but for example, there is a problem that a target computer having embedded hardware for high speed cannot be simulated. Further, in the second conventional example, even though the hardware can be simulated, a simulated instruction that cannot be executed by the target computer is included in the instruction set simulation portion of the simulator. At the stage of incorporating the instruction set, it is necessary to remove the simulated part, and the operation is strictly different, and there is a problem that a malfunction may occur. There is also a problem that it is necessary to prepare a special tool to convert the program into a hardware simulation program.

In each of the conventional examples, the instruction set simulator has a format in which the execution of an instruction is simulated for each instruction. Therefore, the program is interrupted by one instruction and the contents of a large number of memory addresses and a plurality of registers are interrupted. For example, there is a problem that it is necessary to construct a program for sequentially reading each content when it is desired to check the contents.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and is provided in a part different from the instruction set of the target computer itself, at a level different from the program level of the instruction set. It is an object of the present invention to obtain an extended instruction set simulator capable of responding to various user requests by adding a function simulation program or a multi-instruction program that can be freely set by a user without being affected by the user.

[0007]

Means for Solving the Problems] extended instruction set simulator in this invention, in a configuration that executes instructions of the assembler level and target computers in a different instruction set simulator, the target competent
Program code written at the assembler level of the computer
An instruction execution unit for executing over de one instruction, program co
If the code is a user-defined function, this
Pre-processing unit or post-processing unit to decode and execute, and pre-processing unit
Or embedded hardware that operates according to the instructions of the post-processing unit
Controls the operation of the instruction execution unit, pre-processing unit or post-processing unit
Program counter .

Further, the user-defined function is described in C language and then converted.

[0009] Still further, the user-defined function includes an Applicatio
n Write in Program Interface (API)
The hardware resources of the target computer are also shown.

Still further, the user-defined function expresses a multi-step function at an assembler level.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 Simulator-targeted system, with memory directly exchanged by the processor,
A description will be given of a simulator including a peripheral device when a peripheral device other than the register that operates in parallel with the register is incorporated. FIG. 1 is a diagram showing a configuration of a simulator according to the present embodiment, and FIG. 2 is a flowchart showing an operation thereof. In FIG. 1, functions of a conventional instruction set simulator include a data memory 22, a register 23,
A memory 28 for storing a program code, a program counter 27, an instruction execution unit 25, and a command control unit 2
9 is provided, and a preprocessing unit 24 that can be defined by a user is provided at a stage preceding a new one instruction execution unit, and a postprocessing unit 25 that can be defined by a user is provided at a subsequent stage. FIG. 3 is a block diagram showing an example of a hardware embedded system to be simulated, in which a hardware multiplier 30 is used as an example of a simulation target other than the instruction set simulator. The multiplier, which is built-in hardware, operates independently of the processor 27. When a multiplier and a multiplicand are put in the data storage addresses 100a 3a and 101b 3b of the memory 23, the multiplication result is stored in the 102 address 3c. Perform the operation.

When multiplication is added as an external circuit in a processor without a multiplication instruction When a processor implements a multiplier by hardware without having a multiplication instruction, it naturally has no multiplication instruction as an assembler (machine language). Therefore, the simulation of the present system cannot be performed only by the instruction set simulator. The simulator shown in FIG. 1 simulates the hardware multiplier 30, which is a simulation target having the above configuration, as a user-defined function. This is defined separately from the instruction execution level of the instruction set simulator, that is, as a preprocessor or postprocessor, and the instruction code sequence at the assembler level of the instruction set simulator does not need to be changed. The configuration was adopted. A user-defined function in C language is incorporated as a method for the user to extend in the pre-processing unit or the post-processing unit. The function name for preprocessing is pre_func (pre_func
Define the function name for post-processing as post_func (meaning post_func () on source). If the user does not use the extension, this function just returns without doing anything. Incidentally, the extension using the C language is one realization method, and it is also possible to define a new description for the extension separately and realize this.
In this case, FIG. 4 is an expression example of the multiplication function defined by the user in the C language.

The operation of the simulator having the above configuration will be described with reference to FIGS. In FIG. 2, the program code 28 is read in S1, and the operation of the hardware multiplier is performed in the preprocessing unit 24 in S2. First, a user defines a virtual instruction for performing multiplication using a hardware circuit. In this case, the data memory addresses 100 and 101
When the hardware is designed to store the multiplication result and the multiplicand in the memory, the hardware always stores the multiplication result at the address 102, the simulator stores the values in the memories 3a (100) and 3b (101). After setting by the instruction, the result of the multiplication can be used at any time by loading the contents of the 3c address. Preprocessing unit 24
If the user defines the function shown in FIG. 4 using the C language as the preprocessing program to be stored in S2, the processing in S2 performs the above-described multiplication itself. Thereafter, the instruction set is executed by the one-instruction execution unit 25 in S3, and if there is a subsequent program in S5, the simulation is continued.

The pre-processing unit 24 described above or a post-processing unit 25 described below includes an API (Application Program).
A technique of displaying a resource (source) of the system as a ram interface and expressing the resource in the C language as a defining function at the position of the resource can be used.

Embodiment 2 "Program Counter PC
Is larger than 1000, and only when the memory at address 200 is 1, when it is desired to observe the contents of 201 to 210 of the memory, the interactive command control of the normal instruction set simulator is used. Would require very complicated command operations. According to the simulator of the present invention, even in such a case, if the required specifications are collectively described by the user as a post-processing function in the C language and defined, the memory observation under the specified conditions can be easily performed in a batch. Becomes possible. FIG. 5 shows an example in which the program executed in S4 of FIG. 2 to be executed by the post-processing unit 26 in the configuration of FIG. 1 is expressed in C language. The meaning of FIG.
The above PC is 1000 or more, and the value of the memory address 200 is 1
Is a command to read the memories 201 to 210 under the condition of In this operation, in S4 of FIG. 2, the continuous reading operation of the address over the ten addresses described in the C language is performed.

[0016]

As described above, according to the present invention, an additional processing program which can be easily used by a user and performs an operation of directly accessing a peripheral portion by itself, separately from a core program constituted only by an instruction set. Thus, the user can easily simulate the desired operation including the peripheral built-in circuit, and also has the effect of avoiding the trouble associated with reassembly.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an extended instruction set simulator according to each embodiment of the present invention.

FIG. 2 is an operation flowchart of an extended instruction set simulator according to each embodiment of the present invention.

FIG. 3 is a configuration diagram of a simulation target system according to the first embodiment.

FIG. 4 is a diagram illustrating an example in which an operation performed by a preprocessing unit is described in C language in the first embodiment.

FIG. 5 is a diagram illustrating an example in which an operation executed by a post-processing unit is described in C language in the second embodiment.

FIG. 6 is a configuration diagram of a simulator in a first conventional example.

FIG. 7 is a diagram showing an operation concept of a second conventional example.

[Explanation of symbols]

11 Instruction execution part of instruction set simulator, 12
Data memory, 13 registers, 141 instruction execution unit, 1
5 program counters, 16 programs (machine language)
Storage unit, 17 command control unit, 1a 1 instruction fetch, 1b program address, 20 extended instruction set simulator, 22 memory, 23 registers, 24
Pre-processing unit, 25 1 instruction execution unit, 26 Post-processing unit, 27
Program counter, 28 program (machine language) storage unit, 29 command control unit, 2a 1 instruction fetch, 2b program address, 30 hardware multiplier (embedded hardware), 31 program memory, 32 program counter, 33 command control unit , 3a multiplier, 3b multiplicand, 3c multiplication result.

Claims (4)

(57) [Claims] In a configuration in which an assembler-level instruction is executed by an instruction set simulator different from a target computer, the assembler-level instruction of the target computer is provided.
Instruction to execute written program code one instruction at a time
An execution unit, wherein the program code is a user-defined function;
Pre-processing or post-processing that decodes and executes user-defined functions
Unit and built-in that operate according to the instruction of the above pre-processing unit or post-processing unit
Controls the operation of the hardware and the instruction execution unit, pre-processing unit or post-processing unit
An extended instruction set simulator, comprising: 2. The extended instruction set computer according to claim 1 , wherein the user-defined function is described in C language and then converted. 3. The user-defined function is an application program.
2. The extended instruction set computer according to claim 1, wherein the extended instruction set computer is described by m Interface (API), and also indicates hardware resources of the target computer. 4. The extended instruction set computer according to claim 1 , wherein the user-defined function expresses a multi-step function at an assembler level.