JPH11232131A - Testing method for data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make effectively verifiable the transition of all the branching prediction RAMs of multi-level constitution by generating a test instruction group for a branching prediction mechanism of a loop structure in an instruction group generated with random number data as input. SOLUTION: The generation part 202 of the instruction group for the branching prediction mechanism is composed of a general test instruction group generation part 203 and a branching system test instruction group generation part 204. From that and a test instruction detailed information table 209, a test instruction setting part 205 generates the test instruction group 212 for the branching mechanism and an execution initial value 210 by using a random number value generation part 201 for generating a random value. A simulation processing part 206 generates an expected value 213 by using the test instruction group 212 for the branching mechanism and the execution initial value 210. A test instruction execution part 207 executes the instruction to be tested by using the execution initial value 210 and the test instruction group 212 for the branching instruction mechanism. A comparison processing part 208 compares an executed result value 214 sampled from the test instruction execution part 207 with the expected value 213, generates an error message and outputs it to an error message output part 211.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test of a data processing device, and more particularly to a method of randomly generating a test instruction group to test a processing function of a data processing device under test.

[0002]

2. Description of the Related Art As a technique for supporting high performance of a data processing apparatus, a pipeline processing method in which an instruction is divided into several processing stages and each apparatus (unit) processes a specific stage every one machine cycle is used. Widely adopted. Further, in order to smoothly process the pipeline, a branch prediction mechanism that predicts whether a branch condition is satisfied / not satisfied at the time of a branch instruction and determines a precedent instruction in advance is widely used.
The branch prediction mechanism has a multi-level branch prediction RAM for storing a branch state, and predicts whether a branch condition is satisfied / not satisfied with reference to the branch prediction RAM every time a branch-related instruction is executed. This realizes faster instruction transition by branching.

With the improvement of processing performance / high-density mounting, the type of branch state controlled by the above-described branch prediction mechanism, the branch prediction RA
As the number of M increases, a large number of test patterns are executed in order to test various combinations of high-speed logic and branch prediction logic operation incorporated in non-loop-type test instructions to improve processing performance. It has become difficult to achieve effective verification in a short period of time. As a conventional non-loop type data processing test method, for example, there is a technique described in Japanese Patent Application Laid-Open No. 8-166892.

[0004]

In the prior art, a test instruction group that generates random number data as an input is a non-loop type instruction group. Therefore, it is necessary to verify a branch prediction process involving an address at which an instruction is executed. Was unsuitable. Conventionally, in order to solve this, a branch prediction RAM is required before the test is executed.
For example, a method of directly setting a branch state and performing a test was adopted. However, this is a case where the branch prediction RAM is single, and the test of the multi-layer branch prediction RAM is not targeted. This is extended to a plurality of branch prediction RAMs, and it is difficult to set a branch state in these RAMs by a conventional technique and to verify a lowermost branch prediction RAM in which the branch state is difficult to transition even when a test is performed. There is also a problem that the branch prediction RAM cannot be externally set. SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems and to effectively verify transitions of all branch prediction RAMs having a multi-layer structure.

[0005]

SUMMARY OF THE INVENTION The present invention comprises a multi-layered branch prediction RAM by generating a test instruction group for a branch prediction mechanism having a loop structure in an instruction group for generating random number data as an input. This makes it possible to effectively verify the predicted branch prediction logic.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows an embodiment of the configuration and operation of a branch prediction mechanism configured in the data processing apparatus under test. The branch prediction mechanism shown in FIG.
3) It is composed of a branch prediction RAM of two layers of a branch prediction RAM 2 (104). When a branch instruction is selected in the instruction queue in which an instruction is registered in advance in the pipeline processing (101), the branch prediction RAM1 (103)
Is a branch taken prediction, the instruction of the branch taken destination is registered in the instruction queue after the branch instruction. However, the branch state in the branch prediction RAM 2 (104) to be referred to next is the branch not taken prediction, and the branch has already been taken. The branch taken instruction predicted by the prediction RAM 1 (103) and registered in the instruction queue is canceled, and the branch state in the branch prediction RAM 1 (103) is rewritten from the branch taken prediction to the branch not taken prediction (1).
02). As described above, in the branch prediction mechanism, by executing the instruction of the branch prediction destination in advance, it is possible to eliminate the penalty of the instruction execution by the pipeline processing, and to realize the high-speed branch instruction processing.

FIG. 2 is a block diagram of an embodiment of the present invention showing the configuration of a test apparatus of the data processing apparatus under test.
In FIG. 2, the test apparatus uses a random value generation unit (201) that generates a random value, and a general test instruction group generation unit (2).
03) / A branch prediction mechanism instruction group generation unit (202) comprising a branch system test instruction group generation unit (204) and a branch mechanism test instruction group (21) from the test instruction detailed information table (209).
2) and a test instruction setting unit (205) for generating an execution initial value (210); a simulation processing unit for generating an expected value (213) using the branch mechanism test instruction group (212) and the execution initial value (210) (206), execution initial value (21
0) / Using the test instruction group (212) for the branch instruction mechanism,
A test instruction execution unit (207) that executes the instruction under test, and an execution result value (21) extracted from the test instruction execution unit (207).
4) is composed of a comparison processing unit (208) for comparing the expected value (213) with the expected value to generate an error message, and an error message output unit (211).

FIG. 3 is a flowchart showing the processing of the entire test apparatus of FIG. Using the generated random number value (301) as an input, a test instruction detailed information table, a branch mechanism test instruction group, and an execution initial value are generated (302), and the test instruction group instruction is simulated to generate an expected value (303). . Thereafter, the same instruction group is executed on the test target device to obtain an execution result (204), and the execution result value is compared with the expected value to check (3).
05) Generate a mismatched execution result value (306) and output it as an error message (307). The above operation is repeated until the specified number of tests are completed (308).

FIG. 4 is a diagram showing the format of each table used in the present invention. The test instruction detailed information table (403) includes a plurality of branch system test instruction detailed information tables (401) and a general test instruction detailed information table (40).
2), and information in the general test instruction detailed information table (402) includes a test instruction type, an instruction type,
The branch test instruction detailed information table (401) includes, in addition to the information of the general test instruction detailed information table (402), the branch type functioned by the branch system test instruction, A branch destination indicating whether the branch destination branches to the same page or another page, a branch direction indicating the direction of the address of the branch destination, and a run after branch indicating the number of instructions that are sequentially executed and arrive at the address of the test instruction already determined. The effective number, the branch status indicating the taken / not taken, the number of loops tested in the test instruction detailed information table group, the number of instructions in the loop, the test instruction number, and the actual address of the branch destination of the branch instruction that causes the loop are shown. Single loop start address / 2
A first loop end address, a second loop end address indicating the end of the loop, a double loop end address, and a first update register / second update register indicating a register for holding the number of loops; Single-loop comparison register / double-loop comparison register used to compare the update register with a loop exit comparison instruction and exit the loop, single loop counter / 2 indicating loop information
It consists of a heavy loop counter / total number of instructions in the loop.

FIG. 5 shows a branch prediction mechanism based on a double loop test instruction group generated from the test instruction detailed information table (403) shown in FIG. When testing the branch prediction mechanism, the same instruction sequence is duplicated in a double loop.
It is possible to efficiently test the branch state transition of the branch prediction by executing it twice. Test instruction detailed information table (5
01) double loop test instruction group (502)
Are a 重 double loop head instruction which is a branch destination of a 重 double loop, a branch instruction in a loop branching to an instruction sequence in the loop, a ル ー プ double loop exit comparison instruction for forming a loop,
Consists of general instructions. When the double loop test instruction group (502) is tested, the branch state transition of the branch instruction A (503) indicating whether the branch instruction A in the loop is taken or not taken in the loop instruction sequence, and the branch instruction A indicates the state transition and the branch prediction of the branch prediction RAM of the branch prediction processing mechanism by A.
This is an AM state transition (504). The operation of the branch prediction mechanism will be described from the branch state transition (503) of the branch instruction A when the condition of the branch instruction A is satisfied or the condition is not satisfied. When the first execution of the branch instruction A is performed, the branch prediction mechanism determines that the branch is not taken from the value of the branch prediction RAM “00” and tries to execute the instruction ahead of the condition where the condition of the branch instruction A is not taken. In fact, since the branch instruction A is taken, the branch prediction by the branch prediction mechanism becomes a mistake, and the branch instruction A
Then, the instruction at the condition where the condition is not satisfied is canceled, the instruction at the condition where the condition of the branch instruction A is satisfied is executed, and "01" is written to the branch prediction RAM. Next, at the time of execution of the second branch instruction A, the condition is satisfied at the time of the first execution, so the branch prediction mechanism determines that the branch is taken, and executes the instruction ahead of the place where the condition of the branch instruction A is satisfied. However, since the branch instruction A is actually taken, the prediction is a hit. By performing the above operation N times in a loop, it is possible to test all combinations of the branch states of the branch prediction RAM. In the conventional non-loop test instruction, since the instruction is executed only once for the branch instruction A, the branch prediction by the branch prediction mechanism is performed only once. Can not.

FIG. 6 shows the generation (30) of the test instruction group shown in FIG.
It is a flowchart which shows the process of 2). A loop type (601) serving as a basis of the branch prediction mechanism test, a test space (602) used for an instruction group in the loop, a branch type instruction causing a loop, and a branch type branching in the same loop An instruction branch test detailed information table is created (603). The selected instruction is a general instruction (605)
In the case of (1), an instruction type, a function, and the like are determined, a general test information table is created (606), and a register satisfying the instruction function and an initial value are determined from the information table to generate an instruction (60).
7) Yes. If the test instruction type is a branch instruction (605), the branch destination address is used for a branch instruction that causes a loop for the test instruction that is sequentially generated from the already created branch test instruction information detailed table (603). And a test instruction information table number. If the branch instruction is a branch instruction into a loop, the address of the branch instruction is compared with the address of the loop instruction. Is generated, a branch instruction that branches to an address space that is the same page if the address space is a different page is generated (61).
0), the branch instruction is normally looped or a branch is taken /
An instruction for setting a register to be compared with the branch to be not taken and a comparison instruction are generated (611), and the above processing is repeated (609).

FIG. 7 is a flowchart for generating a branch system test instruction detailed information table. When the selected branch-related instruction is a branch instruction for generating a loop (701)
Determines the number of loops and the counter so that the branch prediction state in the branch prediction RAM makes a sufficient transition by the branch prediction mechanism (702), and controls the loop in order to prevent the loop from being broken by a group of instructions in the loop. The register is determined (703), and the address of the branch instruction itself and the branch destination address are determined so that all the entries in the branch prediction RAM operate (704).

[0014]

According to the present invention, it is possible to apply a higher load to the device under test employing the branch prediction mechanism in a high-performance pipeline processing method than in the past, by using the branch prediction mechanism logic. The verification efficiency of the processing device having the branch prediction logic can be improved.

[Brief description of the drawings]

FIG. 1 is a configuration and operation example of a branch prediction mechanism.

FIG. 2 is a block diagram showing a configuration of a test system for performing a test of a data processing device by a test method according to an embodiment of the present invention.

FIG. 3 is a flowchart showing processing of the entire test system of FIG. 2;

FIG. 4 is an example of a data table format used by the test system.

FIG. 5 is an example of a branch loop instruction test and a branch prediction operation generated from the table of FIG. 4;

FIG. 6 is a block diagram illustrating internal processing of a test instruction generation unit in FIG. 2;

FIG. 7 is a flowchart showing generation of a branch-system test instruction in FIG. 2;

[Explanation of symbols]

 Reference Signs List 201 random number generation unit 202 branch prediction mechanism instruction group generation unit 203 general test instruction group generation unit 204 branch system test instruction generation unit 205 test instruction setting unit 206 simulation processing unit 207 test instruction execution unit 208 error message output unit 209 test instruction Group detailed information table 210 Initial execution value 211 Error message 212 Test instruction group for branching mechanism 213 Expected value 214 Execution result value

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yutaka Kodama 1st Horiyamashita, Hadano-shi, Kanagawa Prefecture Inside Hitachi Information Technology Co., Ltd. System Division

Claims (1)

[Claims] 1. A process for generating a test instruction group by using random number data as input, a process for generating an expected value of an execution result of the test instruction group by simulation, and causing the data processing device under test to execute the test instruction group. Processing, comparing the expected value of the execution result created by the simulation with the value of the execution result in the data processing device, and extracting a mismatched instruction when the comparison results in a mismatch, and an error message A test method for generating a test instruction group having a loop-structured test instruction group generation process as the test instruction group generation process, wherein the same branch instruction is executed a plurality of times to thereby execute branching in the pipeline processing method. A method for testing a data processing device, comprising testing a prediction mechanism logic.