WO2018228528A1

WO2018228528A1 - Batch circuit simulation method and system

Info

Publication number: WO2018228528A1
Application number: PCT/CN2018/091483
Authority: WO
Inventors: 肖基诰; 肖铁; 王文杰; 李云鹏; 潘勇
Original assignee: 北京紫光得瑞科技有限公司
Priority date: 2017-06-16
Filing date: 2018-06-15
Publication date: 2018-12-20
Also published as: CN107194115B; CN107194115A

Abstract

The present invention provides a batch circuit simulation method and system. The method comprises: dividing a simulation process of test cases to be simulated into multiple simulation stages; grouping the test cases with the same simulation stage sequentially based on an execution sequence of simulation stages, the same simulation stage being the simulation stage having the same simulation operations and a consistent simulation operation execution sequence; and carrying out uniform simulation for the same simulation stage of the test cases in the same group based on the execution sequence of each simulation stage during the simulation process, and simulating the subsequent simulation stage of each test case in the group on the basis of the simulation result. According to the present invention, by extracting the same simulation stage of test cases, grouping the test cases, and sharing the simulation intermediate result in the group with the same simulation stage, the total time consumed by simulation is reduced, the batch circuit simulation speed is increased greatly, and the simulation efficiency is improved.

Description

Batch circuit simulation method and system

Technical field

The present invention relates to the field of circuit design simulation technologies, and in particular, to a batch circuit simulation method and system.

Background technique

In the early development of chip design, in order to ensure the normal operation of the chip, detailed circuit simulation must be carried out. The simulation speed is one of the key factors that determine whether the simulation task can be completed on time. With the rapid growth of the chip scale, the scale of circuit simulation is also getting larger and larger. Relatively, the time for completing the simulation process is getting longer and longer, and the simulation speed is also slower and slower. In order to speed up the simulation, multiple servers are often used for batch simulation. The current routine of batch circuit simulation is to first compile all the input files of the circuit, generate one or more simulation preparation files, and then simulate based on the simulation preparation files. The whole process is divided into two parts: compiling and emulation, so that although the compile time can be reduced, the entire simulation phase of each test case needs to be completely run, resulting in waste of resources.

Moreover, in the simulation process of large-scale circuits, there are often many similar steps between different test cases, especially in the initialization phase, many test cases are almost the same initial configuration process. For example, in the mobile processor SoC chip design, DDR initialization, NAND Flash initialization, etc. are required before the official test starts, and these initialization processes take a long time. In the current traditional simulation mode, the initialization process of each test case needs to be performed once. Referring to FIG. 1, in the batch simulation method proposed in the prior art, the entire simulation process of each test case is completely executed, which results in a long time and affects the progress of the project.

Moreover, due to limitations of hardware resources, each test case in the simulation process may not all be performed in parallel. Moreover, for the simulation of large-scale circuits, there are hundreds of test cases, and the hardware server resources are limited. Only several simulation processes can be run at the same time. All the above factors are combined, which ultimately leads to long time and speed of simulation. Slow, the simulation efficiency is relatively low.

Summary of the invention

The invention provides a batch circuit simulation method and system, which can reduce the overall simulation time consumption, thereby greatly speeding up the batch circuit simulation speed and improving the simulation efficiency.

In order to solve the above technical problem, the present invention adopts the following technical solutions:

In one aspect of the invention, a method for simulating a batch circuit is provided, the method comprising:

Dividing the simulation process of each test case to be simulated into multiple simulation stages;

Test cases having the same simulation stage are sequentially grouped according to the execution order of each simulation stage, and the same simulation stage is a simulation stage having the same simulation operation and the execution order of each simulation operation is consistent;

In the simulation process, the same simulation phase of each test case in the same group is uniformly simulated according to the execution order of each simulation stage, and the subsequent simulation stages of each test case in the group are simulated separately based on the simulation results.

The simulation process of each test case to be simulated is divided into multiple simulation phases, including:

According to the test function implemented by the test case, the simulation process of each test case to be simulated is divided into multiple simulation stages.

Before the simulation process of each test case to be simulated is divided into multiple simulation stages, the method further includes:

The configuration file corresponding to each test case is set according to the configuration type of each simulation stage in each test case to be simulated.

Wherein, the test cases having the same simulation stage are sequentially grouped according to the execution order of each simulation stage, including:

Parsing the configuration files corresponding to each test case to obtain the configuration type of each simulation stage in each test case;

The test cases to which the simulation stages of the same configuration type in the configuration file belong are divided into the same group according to the execution order of each simulation stage, and the configuration types are used to describe the simulation operations included in the corresponding simulation stage and the execution of each simulation operation. order.

After the test cases having the same simulation stage are sequentially grouped according to the execution order of each simulation stage, the method further includes:

Test cases with the same simulation phase in each group are sub-grouped according to the execution order of each simulation phase.

In another aspect of the present invention, a batch circuit simulation system is further provided, the system comprising:

a dividing module, configured to divide the simulation process of each test case to be simulated into multiple simulation stages;

a grouping module, configured to sequentially group test cases having the same simulation stage according to an execution sequence of each simulation stage, where the same simulation stage is a simulation stage having the same simulation operation and the execution order of each simulation operation is consistent;

The simulation module is used for uniformly simulating the same simulation stage of each test case in the same group according to the execution order of each simulation stage in the simulation process, and performing subsequent simulation of each test case in the group based on the simulation result. The phases are simulated separately.

The dividing module is specifically configured to divide the simulation process of each test case to be simulated into multiple simulation stages according to the test function implemented by the test case.

Wherein, the system further comprises:

a configuration module, configured to set each test according to a configuration type of each simulation phase in each test case to be simulated before the dividing module divides a simulation process of each test case to be simulated into multiple simulation phases The configuration file corresponding to the use case.

The grouping module includes a parsing submodule and a grouping submodule;

The parsing sub-module is configured to parse a configuration file corresponding to each test case to obtain a configuration type of each simulation stage in each test case;

The grouping sub-module is configured to sequentially divide the test cases to which the simulation phase of the configuration type in the configuration file belongs into the same group according to the execution order of each simulation stage, where the configuration type is used to describe the corresponding simulation stage. The simulation operation and the execution order of each simulation operation.

The grouping module is further configured to: after the test cases having the same simulation stage are sequentially grouped according to the execution order of each simulation stage, the same simulation is performed in each group according to the execution order of each simulation stage. The test cases of the stage are sub-grouped.

Compared with the prior art, the main advantages of the technical solution of the present invention are as follows:

The batch circuit simulation method and system provided by the embodiments of the present invention divide the simulation phases of each test case, extract the same simulation phase between each test case, and group the test cases with the same simulation phase to realize The simulation intermediate results of the same simulation stage are shared in the group with the same simulation stage, thereby reducing the overall simulation time, thereby greatly speeding up the batch circuit simulation speed and improving the simulation efficiency.

Other features and advantages of the invention will be set forth in the description which follows, The objectives and other advantages of the invention may be realized and obtained by means of the structure particularly pointed in the appended claims.

The technical solution of the present invention will be further described in detail below through the accompanying drawings and embodiments.

DRAWINGS

Various other advantages and benefits will become apparent to those skilled in the art from a The drawings are only for the purpose of illustrating the preferred embodiments and are not to be construed as limiting. Throughout the drawings, the same reference numerals are used to refer to the same parts. In the drawing:

1 is a simulation flow chart of a batch circuit simulation method proposed in the background art;

2 is a flow chart of a method for simulating a batch circuit according to an embodiment of the present invention;

FIG. 3 is a flowchart of a method for simulating a batch circuit according to another embodiment of the present invention; FIG.

4 is a flow chart of simulation of a batch circuit simulation method according to an embodiment of the present invention;

FIG. 5 is a structural block diagram of a batch circuit simulation system according to an embodiment of the present invention; FIG.

FIG. 6 is a structural block diagram of a batch circuit simulation system according to another embodiment of the present invention.

detailed description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While the embodiments of the present invention have been shown in the drawings, the embodiments Rather, these embodiments are provided so that this disclosure will be more fully understood and the scope of the disclosure will be fully disclosed.

Those skilled in the art will appreciate that all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the invention belongs, unless otherwise defined. It should also be understood that terms such as those defined in a general dictionary should be understood to have meaning consistent with the meaning in the context of the prior art, and will not be idealized or overly formal unless specifically defined. To explain.

FIG. 2 is a flow chart schematically showing a batch circuit simulation method according to an embodiment of the present invention. Referring to FIG. 2, an embodiment of the present invention specifically includes the following steps:

S11. The simulation process of each test case to be simulated is divided into multiple simulation stages.

S12. The test cases having the same simulation stage are sequentially grouped according to the execution order of each simulation stage, and the same simulation stage is a simulation stage having the same simulation operation and the execution order of each simulation operation is consistent.

S13. In the simulation process, the same simulation stage of each test case in the same group is uniformly simulated according to the execution order of each simulation stage, and the subsequent simulation stages of each test case in the group are separately performed on the basis of the simulation result. simulation.

The batch circuit simulation method provided by the embodiment of the present invention extracts the same simulation phase between each test case by dividing each test case into a simulation stage, and groups the test cases having the same simulation stage to realize The simulation intermediate results of the same simulation stage are shared in the same simulation stage group, thereby reducing the overall simulation time consumption, thereby greatly speeding up the batch circuit simulation speed and improving the simulation efficiency.

FIG. 3 is a flow chart schematically showing a method of simulating a batch circuit according to another embodiment of the present invention. Referring to FIG. 3, the batch circuit simulation method provided by the embodiment of the present invention specifically includes the following steps:

S21. Set a configuration file corresponding to each test case according to a configuration type of each simulation phase in each test case to be simulated.

S22. The simulation process of each test case to be simulated is divided into multiple simulation stages according to the test function implemented by the test case.

In the present embodiment, the test cases are grouped according to the test function, but the grouping process of the present invention is not limited to grouping according to the function test, and any equivalent grouping manner falls within the scope of the present invention.

S23. Group test cases having the same simulation stage are sequentially grouped according to the execution order of each simulation stage. Wherein, the same simulation phase is a simulation phase having the same simulation operation and the execution order of each simulation operation is consistent. Step S23 is specifically implemented by the following steps: parsing the configuration files corresponding to the respective test cases, and obtaining the configuration type of each simulation stage in each test case. The test cases to which the simulation stages of the same configuration type in the configuration file belong are divided into the same group according to the execution order of each simulation stage, and the configuration types are used to describe the simulation operations included in the corresponding simulation stage and the execution of each simulation operation. order.

S24. In the simulation process, the same simulation stage of each test case in the same group is uniformly simulated according to the execution order of each simulation stage, and the subsequent simulation stages of each test case in the group are separately performed on the basis of the simulation result. simulation.

Since there are often many similar steps between different test cases, especially in the initialization phase, many test cases are almost the same as the initial configuration process. For example, in the mobile processor SoC chip design, DDR initialization, NAND Flash initialization, etc. are required before the official test starts, and these initialization processes take a long time. Therefore, the technical solution of the present invention will be explained below by taking the initialization simulation process in the test case as a specific embodiment.

In the embodiment of the present invention, the initial simulation process of each test case to be simulated may be separately divided into multiple simulation stages according to the test function implemented by the initialization simulation process in the test case. Specifically, the initialization simulation process in the test case may be divided into a plurality of simulation stages according to the initialization module, and the division of the simulation stage may be implemented based on the initialization step or the initialization time, and the embodiment of the present invention does not specifically limited.

Before the simulation phase is divided into the initialization simulation process, when the test case is created, the configuration file corresponding to each test case needs to be set according to the configuration type of each simulation phase in each test case to be simulated. In this embodiment, the number of specific test cases is seven, which are Test A, Test B, Test C, Test D, Test E, Test F, and Test G. The initialization process of these seven embodiments is divided into four phases: A, B, C, and D. These four phases have 3, 3, 2, and 4 different configuration types, respectively.

When performing the simulation phase division, firstly, the configuration files corresponding to each test case are parsed, and the configuration types of each simulation phase in each test case are obtained. Specifically, the different configurations are numbered by numbers. For example, the configuration types of the phase A are 1, 2, and 3, respectively, and the configuration types of the phase D are 1, 2, 3, and 4, respectively. In this embodiment, the different phases are the same. The configuration represented by the numbered configuration is different. For example, A1 and D1 are two configurations, respectively, and there is no connection between them. The specific configuration of the test case is shown in Table 1:

Table 1 Configuration Table of Test Cases

Then, according to the execution order of each simulation stage, the test cases to which the simulation stages of the same configuration type in the configuration file belong are sequentially divided into the same group, and the configuration types are used to describe the simulation operations included in the corresponding simulation stage and the respective simulation operations. The order of execution. Specifically, the initialization order of the simulation is ABCD in order, so the analysis starts from phase A, and it is found that there are three configuration types at this stage: Test A and Test B are configuration 1, Test C, Test D, Test E are configuration 2, Test F, Test G is configuration 3, so we divide Test A and Test B into Group 1, Test C, Test D and Test E in Group 2, Test F, Test G in Group 3.

In the embodiment of the present invention, after the test cases having the same simulation stage are sequentially grouped according to the execution order of each simulation stage, the batch circuit simulation method further includes the following steps not shown in the figure: Test cases with the same simulation phase in each group are sub-grouped according to the execution order of each simulation phase.

Specifically, continue to analyze down the timeline. For the two test cases in Phase B: Group 1, there is a differentiation. The two configurations are B3 and B2 respectively, then Group 1 ends here, which includes Phase A. Configuration 1, referred to as A1; look at Group 2, which includes test cases C, D, E three, also appeared in phase B differentiation, where the configuration of Test C and Test D is still the same, are B2, but The configuration of Test E is B3. In this regard, we generate a new Group 4 based on Group 2: it includes configuration 2 of phase A and configuration 2 of phase B (referred to as A2+B2), and Group 2 ends here, which includes the stage. Configuration 2 of A (referred to as A2). Looking at Group 3, it includes two tests, Test F and Test G, which are still the same configuration in Phase B, both of which are 1, so Group 3 continues to be valid and not yet finished.

Continue to analyze down the timeline. For phase C: only Group 3 and Group 4 are currently left. First analyze Group 4: Phase C of Test C and Test D are configuration 1, so Group 4 continues to be valid and has not yet ended; For Group 3: Test F and Test G, the configuration of phase C is different, which is 2 and 1, respectively, so Group 3 ends, which includes configuration 3 of phase A and configuration 1 of phase B, referred to as A3+B1;

Continue to analyze down the timeline. For Phase D: Currently only Group 4 is left. Test C and Test D are differentiated in Phase 4 configuration, so Group 4 ends, it includes Group 2, Phase B configuration 2 and Configuration 1 of phase C, referred to as Group 2+A2+B2+C1.

Through the above processing, the following grouping information is obtained:

Group 1: A1

Group 2: A2

Group 3: A3+B1

Group 4: Group 2+B2+C1

For each test case, the final result of the simulation process disassembly is shown in Table 2:

Table 2 Simulation process disassembly table

Test ATest A	Group 1+B3+C1+D4Group 1+B3+C1+D4
Test BTest B	Group 1+B2+C2+D3Group 1+B2+C2+D3
Test CTest C	Group 4+D3Group 4+D3
Test DTest D	Group 4+D2Group 4+D2
Test ETest E	Group 2+B3+C1+D4Group 2+B3+C1+D4
Test F Test F		Group 3+C2+D1Group 3+C2+D1
Test G Test G		Group 3+C1+D3Group 3+C1+D3

This information is stored in text in a specific format for easy use in the simulation process.

In the simulation process, the same simulation phase of each test case in the same group is uniformly simulated according to the execution order of each simulation stage, and the subsequent simulation stages of each test case in the group are simulated separately based on the simulation results. FIG. 4 is a schematic flow chart showing a simulation method of a batch circuit simulation method according to an embodiment of the present invention. According to the above information, Group 1, Group 2, and Group 3 are not dependent on any other simulation process, so the simulation is performed. At the beginning, they can run in parallel; as shown in Figure 4, at the end of Group 2, copy the current simulation process and run Group 4 from the current point in time. When any Group ends, the test cases it depends on can be run. For example, after Group 1 ends, Test A and Test B can copy the simulation process on the basis of Group 1, and start running the remaining simulation phases. After Group 3 is finished, Test F and Test G can be copied on the basis of Group 3. The simulation process starts running the rest of the simulation phase.

It should be noted that the “secondary” in the “secondary packet” proposed in the embodiment of the present invention is not used to define a specific number of groupings, and the case where the test cases in a certain group are grouped multiple times is not excluded. If the test cases after the second grouping in each simulation stage still have the same simulation stage, the grouping is continued, and the same simulation stage of each test case in the same group is uniformly simulated. For example, after grouping Test C, Test D, and Test E for the first time, group 2 is formed, and phase B is formed. Group 2 is grouped into Group 4, D phase, and group 4 is grouped again. It can be seen that the case of multiple times grouping test cases in a certain group falls within the protection scope of the present invention.

In the embodiment of the present invention, all the test cases are divided into several groups, and the test cases in the same group have the same initialization process. First, the same part is uniformly simulated. When the same initialization process is finished, different function point configurations begin to appear between the test cases in the same group. At this time, it is divided into multiple tasks to start execution. This approach significantly reduces redundant initialization processes and reduces overall simulation time.

For the method embodiments, for the sake of simple description, they are all expressed as a series of action combinations, but those skilled in the art should understand that the embodiments of the present invention are not limited by the described action sequence, because the embodiment according to the present invention Some steps can be performed in other orders or at the same time. In the following, those skilled in the art should also understand that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

FIG. 5 is a block diagram showing the structure of a batch circuit simulation system according to an embodiment of the present invention. Referring to FIG. 5, the batch circuit simulation system of the embodiment of the present invention specifically includes a partitioning module 101, a grouping module 102, and a simulation module 103, where:

The dividing module 101 is configured to divide the simulation process of each test case to be simulated into multiple simulation stages;

The grouping module 102 is configured to sequentially group test cases having the same simulation stage according to an execution sequence of each simulation stage, where the same simulation stage is a simulation stage having the same simulation operation and the execution order of each simulation operation is consistent. ;

The simulation module 103 is configured to perform unified simulation on the same simulation phase of each test case in the same group according to the execution order of each simulation phase in the simulation process, and based on the simulation result, The subsequent simulation phases of the test cases are simulated separately.

In an optional embodiment of the present invention, the dividing module 101 is specifically configured to divide the simulation process of each test case to be simulated into multiple simulation stages according to the test function implemented by the test case.

FIG. 6 is a block diagram showing the structure of a batch circuit simulation system according to another embodiment of the present invention. Referring to FIG. 6, the batch circuit simulation system of the embodiment of the present invention specifically includes a configuration module 100, a partitioning module 101, a grouping module 102, and a simulation module 103, where:

The configuration module 100 is configured to set a configuration file corresponding to each test case according to a configuration type of each simulation phase in each test case to be simulated. In this embodiment, before the dividing module 101 divides the simulation processes of the respective test cases to be simulated into multiple simulation phases, respectively, according to the configuration of each simulation phase in each test case to be simulated. Type Set the configuration file corresponding to each test case.

The dividing module 101 is configured to divide the simulation process of each test case to be simulated into multiple simulation stages according to the test function implemented by the test case.

The grouping module 102 is configured to sequentially group test cases having the same simulation stage according to an execution sequence of each simulation stage, where the same simulation stage is a simulation stage having the same simulation operation and the execution order of each simulation operation is consistent. .

Further, the grouping module 102 further includes a parsing submodule and a grouping submodule, wherein:

The parsing sub-module is configured to parse a configuration file corresponding to each test case, and obtain a configuration type of each simulation stage in each test case;

The grouping sub-module is configured to sequentially divide the test cases to which the simulation phase of the configuration type in the configuration file belongs into the same group according to the execution order of each simulation phase, where the configuration type is used to describe the corresponding simulation phase. The simulation operation and the execution order of each simulation operation.

In this embodiment, the grouping module 102 is further configured to: after the test cases having the same simulation stage are sequentially grouped according to the execution order of each simulation stage, each group is performed according to the execution order of each simulation stage. Test cases with the same simulation phase are sub-grouped.

For the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the description of the method embodiment.

The batch circuit simulation method and system provided by the invention divides the simulation phases of each test case, extracts the same simulation phase between each test case, and groups the test cases with the same simulation phase to realize The simulation intermediate results of the same simulation stage are shared in the same simulation stage group, thereby reducing the overall simulation time, especially for large-scale circuit batch simulation, which can save a lot of simulation time, thereby greatly accelerating the batch circuit. Simulation speed to improve simulation efficiency.

The emulation methods and displays provided herein are not inherently related to any particular computer, virtual system, or other device. Various general purpose systems can also be used with the teaching based on the teachings herein. The structure required to construct such a system is apparent from the above description. Moreover, the invention is not directed to any particular programming language. It is to be understood that the invention may be embodied in a variety of programming language, and the description of the specific language has been described above in order to disclose the preferred embodiments of the invention.

In the description provided herein, numerous specific details are set forth. However, it is understood that the embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures, and techniques are not shown in detail so as not to obscure the understanding of the description.

Similarly, the various features of the invention are sometimes grouped together into a single embodiment, in the above description of the exemplary embodiments of the invention, Figure, or a description of it. However, the method disclosed is not to be interpreted as reflecting the intention that the claimed invention requires more features than those recited in the claims. Rather, as the following claims reflect, inventive aspects reside in less than all features of the single embodiments disclosed herein. Therefore, the claims following the specific embodiments are hereby explicitly incorporated into the embodiments, and each of the claims as a separate embodiment of the invention.

Those skilled in the art will appreciate that the modules in the devices of the embodiments can be adaptively changed and placed in one or more devices different from the embodiment. The modules or units or components of the embodiments may be combined into one module or unit or component, and further they may be divided into a plurality of sub-modules or sub-units or sub-components. In addition to such features and/or at least some of the processes or units being mutually exclusive, any combination of the features disclosed in the specification, including the accompanying claims, the abstract and the drawings, and any methods so disclosed, or All processes or units of the device are combined. Each feature disclosed in the specification (including the accompanying claims, the abstract and the drawings) may be replaced by alternative features that provide the same, equivalent or similar purpose.

In addition, those skilled in the art will appreciate that although some embodiments herein include certain features included in other embodiments and not other features, combinations of features of different embodiments are intended to be within the scope of the present invention. And different embodiments are formed. For example, in the claims, any one of the claimed embodiments can be used in any combination.

Those skilled in the art will appreciate that embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.

The present invention has been described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (system), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or FIG. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing device to produce a machine for the execution of instructions for execution by a processor of a computer or other programmable data processing device. Means for implementing the functions specified in one or more of the flow or in a block or blocks of the flow chart.

The computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device. The apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.

These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device. The instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

It is apparent that those skilled in the art can make various modifications and variations to the invention without departing from the spirit and scope of the invention. Thus, it is intended that the present invention cover the modifications and modifications of the invention

Claims

A batch circuit simulation method, characterized in that the method comprises:

Dividing the simulation process of each test case to be simulated into multiple simulation stages;

Test cases having the same simulation stage are sequentially grouped according to the execution order of each simulation stage, and the same simulation stage is a simulation stage having the same simulation operation and the execution order of each simulation operation is consistent;

In the simulation process, the same simulation phase of each test case in the same group is uniformly simulated according to the execution order of each simulation stage, and the subsequent simulation stages of each test case in the group are simulated separately based on the simulation results.
The method according to claim 1, wherein the simulation process of each test case to be simulated is divided into a plurality of simulation phases, respectively, including:

According to the test function implemented by the test case, the simulation process of each test case to be simulated is divided into multiple simulation stages.
The method according to claim 1, wherein before the dividing the simulation process of each test case to be simulated into a plurality of simulation stages, the method further comprises:

The configuration file corresponding to each test case is set according to the configuration type of each simulation stage in each test case to be simulated.
The method according to claim 3, wherein the grouping test cases having the same simulation stage are sequentially grouped according to the execution order of each simulation stage, including:

Parsing the configuration files corresponding to each test case to obtain the configuration type of each simulation stage in each test case;

The test cases to which the simulation stages of the same configuration type in the configuration file belong are divided into the same group according to the execution order of each simulation stage, and the configuration types are used to describe the simulation operations included in the corresponding simulation stage and the execution of each simulation operation. order.
The method according to claim 1, wherein after the test cases having the same simulation stage are sequentially grouped according to the execution order of each simulation stage, the method further includes:

Test cases with the same simulation phase in each group are sub-grouped according to the execution order of each simulation phase.
A batch circuit simulation system, comprising:

a dividing module, configured to divide the simulation process of each test case to be simulated into multiple simulation stages;

a grouping module, configured to sequentially group test cases having the same simulation stage according to an execution sequence of each simulation stage, where the same simulation stage is a simulation stage having the same simulation operation and the execution order of each simulation operation is consistent;

The simulation module is used for uniformly simulating the same simulation stage of each test case in the same group according to the execution order of each simulation stage in the simulation process, and performing subsequent simulation of each test case in the group based on the simulation result. The phases are simulated separately.
The system according to claim 6, wherein the dividing module is specifically configured to divide the simulation process of each test case to be simulated into multiple simulation stages according to the test function implemented by the test case.
The system of claim 6 wherein the system further comprises:

a configuration module, configured to set each test according to a configuration type of each simulation phase in each test case to be simulated before the dividing module divides a simulation process of each test case to be simulated into multiple simulation phases The configuration file corresponding to the use case.
The system according to claim 8, wherein the grouping module comprises a parsing submodule and a grouping submodule;

The parsing sub-module is configured to parse a configuration file corresponding to each test case to obtain a configuration type of each simulation stage in each test case;

The grouping sub-module is configured to sequentially divide the test cases to which the simulation phase of the configuration type in the configuration file belongs into the same group according to the execution order of each simulation stage, where the configuration type is used to describe the corresponding simulation stage. The simulation operation and the execution order of each simulation operation.
The system according to claim 6, wherein the grouping module is further configured to sequentially group test cases having the same simulation stage according to an execution order of each simulation stage, according to each simulation stage. The execution order divides the test cases with the same simulation phase in each group into two groups.