CN106777665A - Improve the method and system of cooperating simulation platform verification efficiency - Google Patents
Improve the method and system of cooperating simulation platform verification efficiency Download PDFInfo
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Abstract
The present invention provides a kind of method and system for improving cooperating simulation platform verification efficiency, and methods described includes：Cooperating simulation platform is set up, the chip to be tested in cooperating simulation platform includes：Several functional units；C model includes：Each functional unit of correspondence chip to be tested, several emulation testing submodels for sequentially forming；Same test and excitation is sent to chip to be tested and C model simultaneously；In simulation process, each emulation testing submodel independently exports simulation result；According to intermediate result emulation logic, and the adjacent next emulation testing submodel of currently emulation testing submodel, the form of the corresponding simulation result of current emulation testing submodel is converted to the identical form of the required input test excitation of emulation submodel adjacent thereto, as the input test excitation of its adjacent emulation submodel and the adjacent corresponding functional unit of emulation submodel.The present invention improves verification efficiency, it is ensured that the uniformity of same test case.
Description
Technical field
The present invention relates to network communication field, more particularly to a kind of method for improving cooperating simulation platform verification efficiency and it is
System.
Background technology
As shown in figure 1, be collaborative simulation Organization Chart of the prior art, its be a kind of chip-scale collaborative simulation operation it is flat
Platform, under the cooperating simulation platform, for chip to be tested, to its all of function, can only do a chip-scale association
With emulation；However, with the raising of chip-scale, the debugging difficulty more and more higher in collaborative simulation, this kind of framework is not suitable for section
The development of skill.
Further, in order to reduce debugging difficulty, in collaborative simulation early stage, with reference to shown in Fig. 2, according to chip to be tested
Whole chip to be tested is divided into subsystem one by one by function, also can be according to same as the C model of chip functions reference
Mode is divided, and by the verification mode of this stratification, the debugging efforts between subsystems can be completed parallel, and
Pinpointed the problems in advance by the debugging of subsystem stage or module level, the workload of later stage chip-scale emulation is reduced, because phase
Lower its debugging difficulty of level where same problem is lower, so as to improve collaborative simulation verification efficiency.
Above-mentioned to treat after test chip divided, the chip to be tested forms chip-scale, subsystem irrespective of size and module
The hierarchical structures such as level；In the prior art, in the cooperating simulation platform of the chip to be tested that should plant hierarchical structure, it is necessary to be every
One subsystem and module to be measured produce excitation respectively, it is difficult to ensure that system testing of the same test case in different stage
In uniformity, and, it is necessary to increase substantial amounts of repeated workload, verification efficiency is low in verification process.
The content of the invention
It is an object of the invention to provide a kind of method and system for improving cooperating simulation platform verification efficiency.
One of to achieve the above object, the method for the raising cooperating simulation platform verification efficiency of an embodiment of the present invention,
Methods described includes：Cooperating simulation platform is set up, the cooperating simulation platform includes：Chip to be tested and correspondence are described to be measured
The C model that examination chip is set up；
The chip to be tested includes：According to several functional units that its function is divided；
The C model includes：Each functional unit of correspondence chip to be tested, several emulation testing submodules for sequentially forming
Type, each emulation testing submodel corresponds each functional unit of chip to be tested；
Same test and excitation is sent to the chip to be tested and the C model simultaneously；
In simulation process, each emulation testing submodel independently exports simulation result；
According to intermediate result emulation logic, and the adjacent next emulation testing submodule of presently described emulation testing submodel
Type, needed for the form of the corresponding simulation result of presently described emulation testing submodel is converted into emulation submodel adjacent thereto
The identical form of the input test excitation asked, as its adjacent emulation submodel and adjacent emulation submodel correspondence
The functional unit input test excitation.
Used as the further improvement of an embodiment of the present invention, the chip to be tested is divided into the layer of subsystem level
Level structure, the functional unit corresponds the subsystems of the chip to be tested.
Used as the further improvement of an embodiment of the present invention, the chip to be tested is divided into the level of module level
Structure, the functional unit corresponds each submodule of the chip to be tested.
Used as the further improvement of an embodiment of the present invention, methods described also includes：
After current emulation testing submodel and corresponding functional unit export simulation result, current emulation testing is judged
Whether the simulation result of submodel is identical with the simulation result of the corresponding functional unit；
If identical, judge the functional unit of current chip to be tested by checking；
If it is different, judging that the functional unit of current chip to be tested fails by checking.
Used as the further improvement of an embodiment of the present invention, methods described also includes：
If judging, the simulation result of current emulation testing submodel is differed with the simulation result of the corresponding functional unit, is tied
Beam is emulated, and exports error information.
One of to achieve the above object, the system of the raising cooperating simulation platform verification efficiency of an embodiment of the present invention,
The system includes：Model construction module, for setting up cooperating simulation platform, the cooperating simulation platform includes：Core to be tested
The C model that piece and the correspondence chip to be tested are set up；
The chip to be tested includes：According to several functional units that its function is divided；
The C model includes：Each functional unit of correspondence chip to be tested, several emulation testing submodules for sequentially forming
Type, each emulation testing submodel corresponds each functional unit of chip to be tested；
Excitation sending module, for sending same test and excitation simultaneously to the chip to be tested and the C model；
Processing module, in simulation process, making each emulation testing submodel independently export simulation result；
According to intermediate result emulation logic, and the adjacent next emulation testing submodule of presently described emulation testing submodel
Type, needed for the form of the corresponding simulation result of presently described emulation testing submodel is converted into emulation submodel adjacent thereto
The identical form of the input test excitation asked, as its adjacent emulation submodel and adjacent emulation submodel correspondence
The functional unit input test excitation.
Used as the further improvement of an embodiment of the present invention, the chip to be tested is divided into the layer of subsystem level
Level structure, the functional unit corresponds the subsystems of the chip to be tested.
Used as the further improvement of an embodiment of the present invention, the chip to be tested is divided into the level of module level
Structure, the functional unit corresponds each submodule of the chip to be tested.
Used as the further improvement of an embodiment of the present invention, the system also includes：Comparing module, for being imitated currently
After true test submodel and corresponding functional unit export simulation result, the imitative of current emulation testing submodel is judged
Whether true result is identical with the simulation result of the corresponding functional unit；
If identical, judge the functional unit of current chip to be tested by checking；
If it is different, judging that the functional unit of current chip to be tested fails by checking.
Used as the further improvement of an embodiment of the present invention, the comparing module is additionally operable to：If judging, current emulation is surveyed
The simulation result of swab model is differed with the simulation result of the corresponding functional unit,
Then terminate emulation, and export error information.
Compared with prior art, the beneficial effects of the invention are as follows：Raising cooperating simulation platform verification efficiency of the invention
Method and system, carry out division and form each functional unit to chip, meanwhile, C model is divided into corresponding each functional unit
Emulation testing submodel, in this way, to reduce the debugging difficulty in test process, meanwhile, in simulation process, according to specific
Form preserves the simulation result of a upper emulation testing submodel, so that the simulation result of each emulation testing submodel is common to
The collaborative simulation verification excitation of chip-scale, subsystem and module, improves verification efficiency, reduces repeated workload, and ensure same
The uniformity of one test case.
Brief description of the drawings
Fig. 1 is a kind of configuration diagram of the cooperating simulation platform of implementation method of prior art；
Fig. 2 is the configuration diagram of the cooperating simulation platform of another embodiment in the prior art；
Fig. 3 is the schematic flow sheet of the method for raising cooperating simulation platform verification efficiency in an embodiment of the present invention；
Fig. 4 is the module diagram of the system of raising cooperating simulation platform verification efficiency in an embodiment of the present invention；
Fig. 5 A are cooperating simulation platform configuration diagrams in a specific example of the invention；
Fig. 5 B to Fig. 5 D are the realizations using one of them sub- simulation model in cooperating simulation platform framework C model shown in Fig. 5 A
Journey schematic diagram.
Specific embodiment
Below with reference to specific embodiment shown in the drawings, the present invention will be described in detail.But these implementation methods are simultaneously
The present invention is not limited, structure that one of ordinary skill in the art is made according to these implementation methods, method or functionally
Conversion is all contained in protection scope of the present invention.
As shown in figure 1, in an embodiment of the present invention, the method for improving cooperating simulation platform verification efficiency, methods described
Including：
S1, cooperating simulation platform is set up, the cooperating simulation platform includes：Chip to be tested and the correspondence chip to be tested
The C model of foundation；The chip to be tested includes：According to several functional units that its function is divided；The C model bag
Include：Each functional unit of correspondence chip to be tested, several emulation testing submodels for sequentially forming, each emulation testing
Model corresponds each functional unit of chip to be tested.
In a preferred embodiment of the invention, the chip to be tested is divided into the hierarchical structure of subsystem level, institute
State the subsystems that functional unit corresponds the chip to be tested.
In a preferred embodiment of the invention, the chip to be tested is divided into the hierarchical structure of module level, described
Functional unit corresponds each submodule of the chip to be tested.
Further, in an embodiment of the present invention, methods described also includes：S2, to the chip to be tested and the C
Model sends same test and excitation simultaneously.
In the specific embodiment of the invention, the verification process of chip to be tested, it will usually according to user's request, respectively for
One entirety of chip to be tested, subsystems and each submodule carry out one-time authentication respectively；In the prior art, it is right
In same chip to be tested, when the entirety to chip is verified, a test and excitation is integrally sent to it；For each height
, it is necessary to corresponding to each subsystem respectively configures different test and excitations when system is verified；And for modules checking when, together
Sample needs to correspond to the different test and excitations of each module configuration respectively；In this way, causing to be divided into chip to be tested hierarchical
After structure, its each test case is inconsistent, and verification efficiency is low；And in the present invention, when chip is divided into subsystem level
Hierarchical structure or after being divided into the hierarchical structure of module level, treating during test chip carries out verification process, it is only necessary to test
When card starts, there is provided a test and excitation, different checking ranks that just can be respectively to same chip to be tested are emulated respectively
Test, will below will be described in detail.
Further, in an embodiment of the present invention, methods described also includes：In S3, simulation process, each emulation testing
Submodel independently exports simulation result；
According to intermediate result emulation logic, and the adjacent next emulation testing submodule of presently described emulation testing submodel
Type, needed for the form of the corresponding simulation result of presently described emulation testing submodel is converted into emulation submodel adjacent thereto
The identical form of the input test excitation asked, as its adjacent emulation submodel and adjacent emulation submodel correspondence
The functional unit input test excitation.In this way, being directed to a certain test case, it is ensured that input to emulation testings at different levels
The being consistent property of test and excitation of submodel and its corresponding functional unit.
In order to make it easy to understand, with reference to shown in Fig. 5 A, a specific example is described by taking network exchanging chip as an example, in order to understand
The present invention.
Under the example, the exchange chip is divided into the hierarchical structure of subsystem level, a pair of the functional unit 1
The corresponding subsystems of the subsystems of the exchange chip, the exchange chip are answered to be followed successively by：Subsystem A1, subsystem
System A2 ... subsystems An；The C model includes：The emulation testing submodule that the subsystems of correspondence exchange chip are sequentially formed
Type, each emulation testing submodel is followed successively by：Emulation testing submodel A1, emulation testing submodel A2 ... emulation testing submodules
Type An；Subsystems transmission message data in the exchange chip.
Same test and excitation A1 is sent simultaneously to the exchange chip and the C model, and the test and excitation is message number
According to.
In simulation process, shown in combination Fig. 5 B, emulation testing submodel A1 and subsystem A1 receives the test simultaneously
Excitation A1, and output simulation result B1, C1 respectively；Simulation result B1 is as shown in panelb；Further, parsing is surveyed with current emulation
The form of the swab model A1 adjacent emulation testing submodel required test and excitations of A2；Will according to intermediate result conversion logic
The form of B1 is converted to the test and excitation S1 with the test submodel required same formats of A2；Under the example, emulation testing
The form of the required test and excitation S1 of model A2 is as shown in Figure 5 C；Further, test and excitation S1 is surveyed as emulation simultaneously
The test and excitation of swab model A2 and subsystem A2.Accordingly, test and excitation S1 is input to correspondence emulation testing submodel
The actuation generator of A2 and subsystem A2, test and excitation S1 is exported as shown in Figure 5 D after the treatment of the actuation generator
Result, the result can be simulated simultaneously test submodel A2 and subsystem A2 read, to carry out emulation testing.So follow
Ring, it is ensured that the test cases at different levels of the subsystem of emulation testing submodels at different levels and correspondence exchange chip are consistent, and improve
Verification efficiency.
Further, in an embodiment of the present invention, methods described also includes：S4, current emulation testing submodel and
After corresponding functional unit exports simulation result, judge that the simulation result of current emulation testing submodel is described with corresponding
Whether the simulation result of functional unit is identical；If identical, judge the functional unit of current chip to be tested by checking；If no
Together, judge that the functional unit of current chip to be tested fails by checking.
In the preferred embodiment for the present invention, if judging the simulation result and the corresponding function of current emulation testing submodel
The simulation result of unit is differed, then terminate emulation, and export error information.
Continue above-mentioned example：Emulation testing submodel A1 and subsystem A1 are exported into simulation result B1, C1 respectively is carried out
Contrast, if the result of B1, C1 is identical, illustrates the subsystem A1 of exchange chip by checking, if it is different, judging that subsystem A1 fails
By checking；In the example, if judging the simulation result of current emulation testing submodel and the emulation of the corresponding functional unit
Result is differed, then terminate emulation, and export error information.If in this way, there is mistake in the design process in exchange chip,
The starting stage of checking can send error information, save the cost of checking, it is easy to the position that authentication error occurs.
With reference to shown in Fig. 4, an embodiment of the present invention, there is provided raising cooperating simulation platform verification efficiency system bag
Include：Model construction module 100, excitation sending module 200, processing module 300, comparing module 400.
Cooperating simulation platform 100 is set up, for setting up cooperating simulation platform, the cooperating simulation platform includes：It is to be tested
The C model that chip and the correspondence chip to be tested are set up；The chip to be tested includes：Divided according to its function
Several functional units；The C model includes：Each functional unit of correspondence chip to be tested, sequentially form several imitate
True test submodel, each emulation testing submodel corresponds each functional unit of chip to be tested.
In a preferred embodiment of the invention, the chip to be tested is divided into the hierarchical structure of subsystem level, institute
State the subsystems that functional unit corresponds the chip to be tested.
In a preferred embodiment of the invention, the chip to be tested is divided into the hierarchical structure of module level, described
Functional unit corresponds each submodule of the chip to be tested.
Further, in an embodiment of the present invention, excitation sending module 200 is used for the chip to be tested and described
C model sends same test and excitation simultaneously.
In the specific embodiment of the invention, the verification process of chip to be tested, it will usually according to user's request, respectively for
One entirety of chip to be tested, subsystems and each submodule carry out one-time authentication respectively；In the prior art, it is right
In same chip to be tested, when the entirety to chip is verified, a test and excitation is integrally sent to it；For each height
, it is necessary to corresponding to each subsystem respectively configures different test and excitations when system is verified；And for modules checking when, together
Sample needs to correspond to the different test and excitations of each module configuration respectively；In this way, causing to be divided into chip to be tested hierarchical
After structure, its each test case is inconsistent, and verification efficiency is low；And in the present invention, when chip is divided into subsystem level
Hierarchical structure or after being divided into the hierarchical structure of module level, treating during test chip carries out verification process, it is only necessary to test
When card starts, there is provided a test and excitation, different checking ranks that just can be respectively to same chip to be tested are emulated respectively
Test, will below will be described in detail.
Further, in an embodiment of the present invention, processing module 300 is used in simulation process, surveys each emulation
Swab model independently exports simulation result；According to intermediate result emulation logic, and presently described emulation testing submodel phase
Adjacent next emulation testing submodel, by the form of the corresponding simulation result of presently described emulation testing submodel be converted to
The identical form of its adjacent required input test excitation of emulation submodel, as its adjacent emulation submodel with
And the input test excitation of the adjacent corresponding functional unit of emulation submodel.In this way, a certain test case is directed to, can be with
Guarantee inputs to emulation testing submodels at different levels and the being consistent property of test and excitation of its corresponding functional unit.
In order to make it easy to understand, with reference to shown in Fig. 5 A, a specific example is described by taking network exchanging chip as an example, in order to understand
The present invention.
Under the example, the exchange chip is divided into the hierarchical structure of subsystem level, a pair of the functional unit 1
The corresponding subsystems of the subsystems of the exchange chip, the exchange chip are answered to be followed successively by：Subsystem A1, subsystem
System A2 ... subsystems An；The C model includes：The emulation testing submodule that the subsystems of correspondence exchange chip are sequentially formed
Type, each emulation testing submodel is followed successively by：Emulation testing submodel A1, emulation testing submodel A2 ... emulation testing submodules
Type An；Subsystems transmission message data in the exchange chip.
Same test and excitation A1 is sent simultaneously to the exchange chip and the C model, and the test and excitation is message number
According to.
In simulation process, shown in combination Fig. 5 B, emulation testing submodel A1 and subsystem A1 receives the test simultaneously
Excitation A1, and output simulation result B1, C1 respectively；Simulation result B1 is as shown in panelb；Further, parsing is surveyed with current emulation
The form of the swab model A1 adjacent emulation testing submodel required test and excitations of A2；Will according to intermediate result conversion logic
The form of B1 is converted to the test and excitation S1 with the test submodel required same formats of A2；Under the example, emulation testing
The form of the required test and excitation S1 of model A2 is as shown in Figure 5 C；Further, test and excitation S1 is surveyed as emulation simultaneously
The test and excitation of swab model A2 and subsystem A2.Accordingly, test and excitation S1 is input to correspondence emulation testing submodel
The actuation generator of A2 and subsystem A2, test and excitation S1 is exported as shown in Figure 5 D after the treatment of the actuation generator
Result, the result can be simulated simultaneously test submodel A2 and subsystem A2 read, to carry out emulation testing.So follow
Ring, it is ensured that the test cases at different levels of the subsystem of emulation testing submodels at different levels and correspondence exchange chip are consistent, and improve
Verification efficiency.
Further, in an embodiment of the present invention, comparing module 400 is used for：Current emulation testing submodel and with
After its corresponding functional unit exports simulation result, the simulation result and the corresponding work(of current emulation testing submodel are judged
Whether the simulation result of energy unit is identical；If identical, judge the functional unit of current chip to be tested by checking；If it is different,
Judge that the functional unit of current chip to be tested fails by checking.
In the preferred embodiment for the present invention, if judging the simulation result and the corresponding function of current emulation testing submodel
The simulation result of unit is differed, then terminate emulation, and export error information.
Continue above-mentioned example：Emulation testing submodel A1 and subsystem A1 are exported into simulation result B1, C1 respectively is carried out
Contrast, if the result of B1, C1 is identical, illustrates the subsystem A1 of exchange chip by checking, if it is different, judging that subsystem A1 fails
By checking；In the example, if judging the simulation result of current emulation testing submodel and the emulation of the corresponding functional unit
Result is differed, then terminate emulation, and export error information.If in this way, there is mistake in the design process in exchange chip,
The starting stage of checking can send error information, save the cost of checking, it is easy to the position that authentication error occurs.
In sum, the method and system for improving cooperating simulation platform verification efficiency of the invention, divide to chip
Each functional unit is formed, meanwhile, C model is divided into the emulation testing submodel of each functional unit of correspondence, in this way, to drop
Debugging difficulty in low test process, meanwhile, in simulation process, a upper emulation testing submodule is preserved according to specific form
The simulation result of type, so that the simulation result of each emulation testing submodel is common to the association of chip-scale, subsystem and module
Encouraged with simulating, verifying, improve verification efficiency, reduce repeated workload, and ensure the uniformity of same test case.
For convenience of description, it is divided into various modules with function during description apparatus above to describe respectively.Certainly, this is being implemented
The function of each module can be realized in same or multiple softwares and/or hardware during invention.
Device embodiments described above are only schematical, wherein the module illustrated as separating component
Can be or may not be physically separate, the part shown as module can be or may not be physics mould
Block, you can with positioned at a place, or can also be distributed on multiple mixed-media network modules mixed-medias.It can according to the actual needs be selected
In some or all of module realize the purpose of present embodiment scheme.Those of ordinary skill in the art are not paying creation
Property work in the case of, you can to understand and implement.
It should be understood that, although the present specification is described in terms of embodiments, but not each implementation method only includes one
Individual independent technical scheme, this narrating mode of specification is only that for clarity, those skilled in the art will should say
Used as an entirety, technical scheme in each implementation method can also be through appropriately combined, and forming those skilled in the art can for bright book
With the other embodiment for understanding.
Those listed above is a series of to be described in detail only for feasibility implementation method of the invention specifically
Bright, they simultaneously are not used to limit the scope of the invention, all equivalent implementations made without departing from skill spirit of the present invention
Or change should be included within the scope of the present invention.
Claims (10)
1. it is a kind of improve cooperating simulation platform verification efficiency method, it is characterised in that methods described includes：
Cooperating simulation platform is set up, the cooperating simulation platform includes：Chip to be tested and the correspondence chip to be tested are built
Vertical C model；
The chip to be tested includes：According to several functional units that its function is divided；
The C model includes：Each functional unit of correspondence chip to be tested, several emulation testing submodules for sequentially forming
Type, each emulation testing submodel corresponds each functional unit of chip to be tested；
Same test and excitation is sent to the chip to be tested and the C model simultaneously；
In simulation process, each emulation testing submodel independently exports simulation result；
According to intermediate result emulation logic, and the adjacent next emulation testing submodule of presently described emulation testing submodel
Type, needed for the form of the corresponding simulation result of presently described emulation testing submodel is converted into emulation submodel adjacent thereto
The identical form of the input test excitation asked, as its adjacent emulation submodel and adjacent emulation submodel correspondence
The functional unit input test excitation.
2. it is according to claim 1 improve cooperating simulation platform verification efficiency method, it is characterised in that
The chip to be tested is divided into the hierarchical structure of subsystem level, and the functional unit corresponds described to be tested
The subsystems of chip.
3. it is according to claim 1 improve cooperating simulation platform verification efficiency method, it is characterised in that
The chip to be tested is divided into the hierarchical structure of module level, and the functional unit corresponds the core to be tested
Each submodule of piece.
4. it is according to claim 1 improve cooperating simulation platform verification efficiency method, it is characterised in that methods described is also
Including：
After current emulation testing submodel and corresponding functional unit export simulation result, current emulation testing is judged
Whether the simulation result of submodel is identical with the simulation result of the corresponding functional unit；
If identical, judge the functional unit of current chip to be tested by checking；
If it is different, judging that the functional unit of current chip to be tested fails by checking.
5. piece according to claim 4 method for improving cooperating simulation platform verification efficiency, it is characterised in that methods described
Also include：
If judging, the simulation result of current emulation testing submodel is differed with the simulation result of the corresponding functional unit, is tied
Beam is emulated, and exports error information.
6. it is a kind of improve cooperating simulation platform verification efficiency system, it is characterised in that the system includes：
Model construction module, for setting up cooperating simulation platform, the cooperating simulation platform includes：Chip to be tested and correspondence
The C model that the chip to be tested is set up；
The chip to be tested includes：According to several functional units that its function is divided；
The C model includes：Each functional unit of correspondence chip to be tested, several emulation testing submodules for sequentially forming
Type, each emulation testing submodel corresponds each functional unit of chip to be tested；
Excitation sending module, for sending same test and excitation simultaneously to the chip to be tested and the C model；
Processing module, in simulation process, making each emulation testing submodel independently export simulation result；
According to intermediate result emulation logic, and the adjacent next emulation testing submodule of presently described emulation testing submodel
Type, needed for the form of the corresponding simulation result of presently described emulation testing submodel is converted into emulation submodel adjacent thereto
The identical form of the input test excitation asked, as its adjacent emulation submodel and adjacent emulation submodel correspondence
The functional unit input test excitation.
7. it is according to claim 6 improve cooperating simulation platform verification efficiency system, it is characterised in that
The chip to be tested is divided into the hierarchical structure of subsystem level, and the functional unit corresponds described to be tested
The subsystems of chip.
8. it is according to claim 6 improve cooperating simulation platform verification efficiency system, it is characterised in that
The chip to be tested is divided into the hierarchical structure of module level, and the functional unit corresponds the core to be tested
Each submodule of piece.
9. it is according to claim 6 improve cooperating simulation platform verification efficiency system, it is characterised in that
The system also includes：Comparing module, for equal in current emulation testing submodel and corresponding functional unit
After output simulation result, judge the simulation result of current emulation testing submodel is with the simulation result of the corresponding functional unit
It is no identical；
If identical, judge the functional unit of current chip to be tested by checking；
If it is different, judging that the functional unit of current chip to be tested fails by checking.
10. it is according to claim 9 improve cooperating simulation platform verification efficiency system, it is characterised in that
The comparing module is additionally operable to：If judging the simulation result and the corresponding functional unit of current emulation testing submodel
Simulation result is differed, then terminate emulation, and export error information.
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| CN107194115A (en) * | 2017-06-16 | 2017-09-22 | 北京得瑞领新科技有限公司 | A kind of mass circuit emulation method and system |
| CN108802600A (en) * | 2018-06-15 | 2018-11-13 | 郑州云海信息技术有限公司 | A kind of integrated circuit verification system and method based on FPGA |
| CN113032202A (en) * | 2021-03-26 | 2021-06-25 | 上海阵量智能科技有限公司 | Chip verification method, system, device, computer equipment and storage medium |
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| WO2018228528A1 (en) * | 2017-06-16 | 2018-12-20 | 北京紫光得瑞科技有限公司 | Batch circuit simulation method and system |
| CN108802600A (en) * | 2018-06-15 | 2018-11-13 | 郑州云海信息技术有限公司 | A kind of integrated circuit verification system and method based on FPGA |
| CN113032202A (en) * | 2021-03-26 | 2021-06-25 | 上海阵量智能科技有限公司 | Chip verification method, system, device, computer equipment and storage medium |
| CN113032202B (en) * | 2021-03-26 | 2024-03-05 | 上海阵量智能科技有限公司 | Chip verification method, system, device, computer equipment and storage medium |
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