JP3955843B2 - Microprocessor parallel simulation system - Google Patents

Description

  The present invention relates to a microprocessor parallel simulation system.

  When developing a system including an SOC (System On Chip), it may be necessary to perform performance evaluation and operation verification of the entire system including software before the completion of the target SOC in some processes. In addition, when performing performance evaluation and operation verification with high accuracy, it is necessary to perform a CA (Cycle Accurate) simulation that faithfully reproduces the behavior of the hardware mechanism at the clock level.

  On the other hand, the simulation execution speed in CAS (Cycle Accurate Simulation) requires an actual execution time of about 5000 to 10000 times when a 1-CPU simulation platform is used when the target microprocessor has high performance. There is. For this reason, various studies have been made on speeding up the simulator.

  By the way, in general, as a method for ending a long simulation in a short time, the entire simulation is divided into several parts according to some criteria, and a plurality of computers (simulation nodes) are used to perform the simulation of the plurality of partial simulations. It is possible to parallelize the implementation. However, when simulating the SOC at the CA level, the parallel overhead of the simulation of a plurality of parts by spatial division (for example, by dividing the SOC for each component) increases the communication overhead between the components. End up. At this time, it is difficult to obtain the effect of speeding up the simulation.

  Further, when performing time division (for example, dividing a simulation for each appropriate number of instructions), it is difficult to ensure continuity in the time direction. Surprisingly, it is extremely difficult to ensure the accuracy of simulation results.

  An object of the present invention is to provide a parallel simulation system that performs high-speed and accurate simulation while temporally dividing the CAS of the microprocessor as described above.

The present invention has been made to achieve the above object. A parallel simulation system for a microprocessor according to the present invention includes:
A parallel simulation system for a microprocessor including a plurality of P (P is a natural number of 2 or more) simulation nodes connected by a predetermined network,
Division points from all instruction sequences in the simulation target system to p (p is a natural number and p ≧ P) partial instruction sequences are set, and each division instruction is used as an initial value for scheduling simulation of each partial instruction sequence. For a microprocessor in which a logical state and a virtual internal state of a microprocessor at a point are given, and scheduling simulation of each partial instruction sequence is performed by dividing them into P simulation nodes using these initial values. In a parallel simulation system,
For the i (1 ≦ i ≦ p−1) -th partial instruction sequence, a first number of instruction sequences of a certain number (k) further from the last instruction in the partial instruction sequence at the first simulation node that performs the scheduling simulation. Subsequent simulation means for performing scheduling simulation subsequently,
The state of the instruction scheduling mechanism in the first simulation node at the time when the scheduling simulation of a certain number of instruction sequences performed subsequently is finished is the (i + 1) th following the i-th partial instruction sequence. Transmission means for transmitting to the second simulation node for performing the scheduling simulation for the th partial instruction sequence;
The second simulation node performs a scheduling simulation of the instruction sequence from the top of the (i + 1) th partial instruction sequence to the predetermined number, and stores a state of the instruction scheduling mechanism at that time;
The state of the instruction scheduling mechanism transmitted by the transmission unit and the state of the instruction scheduling mechanism stored by the storage unit are compared to verify the validity of the scheduling simulation performed at the own node. Comparison verification means in two simulation nodes .

  By utilizing the present invention, it is possible to increase the speed and efficiency of a parallel simulation system for a microprocessor according to the number of simulation nodes.

  Hereinafter, preferred embodiments according to the present invention will be described with reference to the drawings.

  FIG. 6 shows a schematic diagram of a hardware configuration in which the parallel simulation system 2 according to the preferred embodiment of the present invention operates. In FIG. 6, a plurality of computers 4 are connected to each other via a LAN 6. The computer 4 may be an ordinary workstation or personal computer. As will be explained later, these individual computers 4 are simulation nodes which simulate each of the time-divided (microprocessor) CAS's (especially in the scheduling simulation).

First, in this specification, CAS is (a) “instruction simulation” for simulating the logical behavior of an instruction,
(B) It is divided into “scheduling simulation” for simulating the instruction scheduling mechanism. Here, it is obvious to those skilled in the art that the former (a) can be executed at a time cost of about 1/100 of the latter. Therefore, the entire simulation can be speeded up by executing the latter (b) in parallel.

  In the parallel simulation system according to the preferred embodiment of the present invention, CAS scheduling simulation is parallelized. That is, the instruction sequence to be simulated is divided in the time direction to obtain several partial instruction sequences, and the instruction scheduling for each partial instruction sequence is executed in parallel. The flow of scheduling simulation processing in the parallel simulation system will be described below.

≪Scheduling simulation process flow≫
<< 1 >> A “command simulation” is performed on the performance verification target system (including the SOC) in advance. As a result, when the total number of executed (simulated) instructions is N and the executed instruction sequence is I (1), I (2),... I (N), the instruction sequence is , A plurality of (here, p) partial instruction sequences {S (1), S (2),. . . , S (p)}.

S (1) = {I (s ₁ = 1),. . . , I (t ₁ )},
S (2) = {I (s ₂ = t ₁ +1),. . . , I (t ₂ )},
・
・
S (p−1) = {I (s _p−1 = t _p−2 +1),. . . , I (t _p-1 )},
S (p) = {I (s _p = t _p−1 +1),. . . , I (t _p = N)}

A method of determining the number of divisions p and the individual division points t _i (1 ≦ i ≦ p−1) will be described later (<< instruction sequence division method >>). Also, division into "instruction simulation", and a partial instruction strings described above may be performed in any computer, for example, in FIG. 6 may be performed by one of the simulation node P _1.

  << 2 >> Next, p partial instruction sequences S (1), S (2),. . . The “scheduling simulation” for S (p) is executed in parallel by P (≦ p) simulation nodes (see FIG. 6).

Partial instruction sequence S (i) = {I (s _i ),. . . , I (t _i )} first acquires the microprocessor's logical state A (i) at the start of execution of I (s _i ). Here, the “microprocessor logical state A (i)” is a value of a register, a memory, or the like related to the microprocessor when the instruction (simulation) is advanced to I ( t _i−1 ). The acquisition of the logical state is assumed to be obtained in one of the following two procedures, and any procedure may be used.
(Procedure 1): In the instruction simulation of << 1 >> above, when the last instruction I (t _i ) of each partial instruction sequence S ( _i ) is executed, the logical state A ( i + 1 ) is saved.
(Procedure 2): Prior to the scheduling simulation of S (i), the instruction simulation regarding all the instructions I (1) to I (t _i-1 ) preceding it is performed to obtain the logical state A (i).

The logical state of the microprocessor is assumed to be A (i) obtained, and the state of the instruction scheduling mechanism is assumed to be a virtual initial state. Then, the instruction scheduling of the partial instruction sequence is changed from I (s _i ) to I (T _i ) to I (t _i + k)
Do. This “virtual initial state” may be, for example, a state in which no instruction exists in the instruction pipeline.

  Here, “k” is a portion for performing scheduling simulations redundantly between a simulation node in charge of S (i) and a simulation node in charge of S (i + 1) in order to verify the validity of instruction scheduling. This is the length (constant) of the instruction sequence.

In FIG.
・ Scheduling simulation is duplicated between the simulation node in charge of S (1) and the simulation node in charge of S (2),
A state in which a scheduling simulation is duplicated between the simulation node in charge of S (2) and the simulation node in charge of S (3), and
A schematic illustration of a scheduling simulation overlapping between a simulation node in charge of S (3) and a simulation node in charge of S (4) is shown.
In Figure 2, the simulation node in charge of S (1) and the overlapping portion (for example) is _{P 1,} the simulation node in charge of the S (2) and overlapping parts are (for example) a _{P 2,} S (3) and simulation node in charge of the overlapping portion (for example) a P _3, the simulation node in charge of the S (4) and overlapping parts are the (for example) is a P _4, shown schematically.

<< 3 >> The simulation node in charge of the partial instruction sequence S (i−1) (i> 2) “instruction scheduling at the time when the last instruction I (t _i−1 + k) in charge is input to the instruction scheduling mechanism. The mechanism state M (t _i−1 + k) ”is transmitted to the simulation node in charge of the partial instruction sequence S (i) via the LAN 6 ((a) in FIG. 3). (To be precise, as described below, the states M (t _i-2 + k) and M ′ (s _i−1 + k−1) transmitted from the simulation node in charge of S (i−2) Will be communicated after completing the comparison process and the conditionally accompanying process.)

The simulation node in charge of S (i) has the instruction scheduling mechanism at the time when the instruction I (s _i + k−1) = I (t _i−1 + k) is input to the instruction scheduling mechanism in the process of the scheduling simulation. The state M ′ (s _i + k−1) is stored and compared with the state M (t _i−1 + k) of the instruction scheduling mechanism transmitted from the simulation node in charge of the above S (i−1). ((A) in FIG. 3).

<< 4 >> If the state comparison of the instruction scheduling mechanism in << 3 >> above matches, the scheduling simulation for S (i) is valid. Therefore, the behavior (for example, the number of execution clocks) after I (s _i + k−1) is input to the instruction scheduling mechanism is a partial result of the scheduling simulation, and the simulation node in charge of S (i) is in the state M ( t _i + k) is transmitted to the simulation node in charge of S (i + 1) via the LAN 6 ((c) in FIG. 3).

If they do not match, the simulation node in charge of S (i) uses the instruction scheduling mechanism state M (t _i-1 + k) transmitted from the node in charge of S (i−1) as the initial state, and I The scheduling simulation after (s _i + k−1) is performed again. Then, the re-execution result is set as a partial result, and the state M (t _i + k) obtained by the re-execution is transmitted to the simulation node in charge of S (i + 1) via the LAN 6.

  << 5 >> The state transmission processing of the instruction scheduling mechanism in the above << 3 >> and << 4 >> is exceptional in the simulation node in charge of the first and last partial instruction sequences S (1) and S (p). It will be a thing.

That is, the simulation node in charge of S (1) does not receive state transmission from other simulation nodes. That is, the scheduling simulation here is unconditionally valid, and M (t ₁ + k) is transmitted to the simulation node in charge of S (2) without waiting for state transmission from other simulation nodes (FIG. 1). I (t ₁ ), see I (t ₁ + k) part).

On the other hand, the simulation node in charge of S (p) does not transmit the state to other simulation nodes. Therefore, the state M (t _p−1 + k) is compared with the state M ′ (s _p + k−1), and if they match, the entire scheduling simulation is completed assuming that a valid result is obtained. If they do not match, the simulation node in charge of S (p) sets the state M (t _p−1 + k) as the initial state, performs the scheduling simulation after I (s _p + k−1) again, and obtains a valid result. And complete the entire scheduling simulation.

  << 6 >> Thus, the scheduling simulation process is completed.

≪ Instruction sequence division method ≫
The instruction sequence division number p for creating the partial instruction sequence can be arbitrarily determined. It is desirable that p ≧ P with respect to the number P of simulation nodes that execute the scheduling simulation in parallel. Furthermore, it is desirable that p is a constant multiple of P for load balancing on the simulation node.

  In addition, when p = cP, the value of the constant c is decreased to reduce the number of occurrences of state mismatch (that is, mismatch in state comparison of instruction scheduling mechanism in << 3 >> of << Scheduling simulation process flow >>). It is possible to envisage a first method that reduces the re-execution time when c is increased and a state mismatch occurs. Whether or not to select one of them can be appropriately determined according to the structure of the microprocessor to be simulated, the number of nodes p, and the like.

  Further, it is possible to adopt a division method in which the length of a partial instruction sequence and a method for selecting a division point are determined in advance, and the entire instruction sequence is divided at a position that meets the above conditions while starting from the beginning. At this time, before the total number N of instructions in the entire instruction sequence is determined, the number of instructions is divided.

As described above, the division point t _i of the partial instruction sequence is determined so that the length t _i −s _i +1 of the partial instruction sequence is substantially constant from the viewpoint of load balancing to the simulation node. Is desirable. On the other hand, in order to reduce the probability of state mismatch in the state comparison of the scheduling mechanism, it is possible to select a division point where mismatch is unlikely to occur. For example, if an instruction that causes an event in which instruction input to the instruction scheduling mechanism is delayed, such as an instruction cache miss or a branch prediction miss, is selected as a division point, it can be easily imagined that mismatches are less likely to occur due to considerable overlapping execution. However, this is because the initial value of the virtual internal state of the scheduling simulation of each partial instruction sequence is substantially similar to the internal state when the branch prediction error occurs (for example, the pipeline is empty, etc.). Such division points can be found with high accuracy and reliability only by performing instruction simulation.

  Further, if the length “k” of the partial instruction sequence to be executed in duplicate is increased, it becomes difficult to cause a state mismatch in the state comparison of the scheduling mechanism, and if it is reduced, time loss due to the duplicate execution is reduced. Therefore, the length “k” can be appropriately set according to the structure of the microprocessor to be simulated, the number of nodes P, the number of divisions p, the method of selecting division points, and the like.

≪About another processing when a state mismatch occurs in the state comparison of the instruction scheduling mechanism≫
In the above description, when a state mismatch occurs in the state comparison of the instruction scheduling mechanism, the simulation node in charge of S (i) transmits the state M (t of the instruction scheduling mechanism transmitted from the simulation node in charge of S (i-1). The scheduling simulation after I (s _i + k−1) is performed again with _i−1 + k) as the initial state again. When such a mismatch occurs, the simulation node in charge of S (i-1) performs a scheduling simulation from I (t _i-1 + k) = I (s _i + k-1) to I (t _i + k) as it is. The processing procedure may be such that the state M (t _i + k) obtained is transmitted to the simulation node in charge of S (i + 1) via the LAN 6.

In FIG. 4, the simulation node P _{2 in} charge of S (2) does not change the state M (t ₂ + k) and the state M ′ (s ₃ + k−1), and then continues as I (t ₂ + k ) = I (s ₃ + k-1) to I (t ₃ + k) and subsequent simulations are performed, and the state M (t ₃ + k) is obtained schematically by the dotted line part in (A). ing.

In FIG. 5, in an instruction scheduling simulation system, four simulation nodes (P ₁ , P ₂ , P ₃ , P ₄ ) are provided, the instruction sequence is divided into 16 parts, and each of the simulation nodes is assigned with 4 parts of them. Is shown schematically. Split by a straight line that indicates the instruction sequence of the top, for example, (1) are attached, shows that assigned to P _1. Here, in FIG. 4 above, if use of state inconsistency at the time of occurrence procedure, for example, if a mismatch occurs in dividing the simulation node P _3, to continue the division partial simulation node P ₂ Will be implemented. Therefore, if the overall processing time is overviewed, P ₁ , P _3, and P ₄ are completed by the processing for four divisions, but only P ₂ is processed by one division. In FIG. 5, it is indicated by a dotted arrow (B). In other words, if the number of instruction strings is considerably increased compared to the number of simulation nodes, the overall processing time is not significantly extended even if the above-mentioned state mismatch occurs.

A state in which a scheduling simulation is duplicated between the simulation node in charge of the partial instruction sequence S (1) and the simulation node in charge of the partial instruction sequence S (2), the simulation node in charge of the partial instruction sequence S (2) and the partial instruction Duplicate scheduling simulation with the simulation node in charge of the sequence S (3), and overlap between the simulation node in charge of the partial command sequence S (3) and the simulation node in charge of the partial command sequence S (4) A schedule simulation is schematically shown. Simulation node in charge of the partial instruction strings S (1) and overlapping portion is P _1, the simulation node in charge of the partial instruction strings S (2) and overlapping portion is P _2, partial instruction strings S (3) and simulation node in charge of the overlapping portion is P _3, the simulation node in charge of partial instruction strings S (4) and the overlapping portion is P _4, shown schematically. The state in which the state of the instruction scheduling mechanism in one simulation node is transmitted to another simulation node and compared with the state there is schematically shown. After the simulation node P _{2 in} charge of the partial instruction sequence S (2) has generated a mismatch in the comparison between the state M (t ₂ + k) and the state M ′ (s ₃ + k−1), I (t ₂ + k) It is schematically shown by a dotted line portion that a scheduling simulation from I = s (s ₃ + k−1) to I (t ₃ + k) is performed and the state M (t ₃ + k) is obtained. In an instruction scheduling simulation system, it is schematically shown that four simulation nodes (P ₁ , P ₂ , P ₃ , P ₄ ) are provided, an instruction sequence is divided into 32, and each of the simulation nodes is assigned with 4 of them. Shown in 1 is a schematic diagram of a hardware configuration in which a parallel simulation system according to a preferred embodiment of the present invention operates.

Explanation of symbols

2 parallel simulation system, 4 computer, 6 LAN (Local Area Network).

Claims (4)

A parallel simulation system for a microprocessor including a plurality of P (P is a natural number of 2 or more) simulation nodes connected by a predetermined network,
Division points from all instruction sequences in the simulation target system to p (p is a natural number and p ≧ P) partial instruction sequences are set, and each division instruction is used as an initial value for scheduling simulation of each partial instruction sequence. For a microprocessor in which a logical state and a virtual internal state of a microprocessor at a point are given, and scheduling simulation of each partial instruction sequence is performed by dividing them into P simulation nodes using these initial values. In a parallel simulation system,
For the i (1 ≦ i ≦ p−1) -th partial instruction sequence, a first number of instruction sequences of a certain number (k) further from the last instruction in the partial instruction sequence at the first simulation node that performs the scheduling simulation. Subsequent simulation means for performing scheduling simulation subsequently,
The state of the instruction scheduling mechanism in the first simulation node at the time when the scheduling simulation of a certain number of instruction sequences performed subsequently is finished is the (i + 1) th following the i-th partial instruction sequence. Transmission means for transmitting to the second simulation node for performing the scheduling simulation for the th partial instruction sequence;
The second simulation node performs a scheduling simulation of the instruction sequence from the top of the (i + 1) th partial instruction sequence to the predetermined number, and stores a state of the instruction scheduling mechanism at that time;
The state of the instruction scheduling mechanism transmitted by the transmission unit and the state of the instruction scheduling mechanism stored by the storage unit are compared to verify the validity of the scheduling simulation performed at the own node. A parallel simulation system for a microprocessor, comprising: comparison verification means in two simulation nodes . The comparison verification unit in the second simulation node compares the state of the instruction scheduling mechanism transmitted by the transmission unit with the state of the instruction scheduling mechanism stored by the storage unit, and a mismatch has occurred. In case,
In the first simulation node, a second subsequent simulation that performs scheduling simulation for the subsequent instruction sequence to the end of the (i + 1) th partial instruction sequence and to the predetermined number of instruction sequences thereafter. Means,
The state of the instruction scheduling mechanism in the first simulation node at the time of the execution result of the second subsequent simulation means is the (i + 2) th (following the (i + 1) th partial instruction sequence) (provided that 1 at this time) The parallel transmission for the microprocessor according to claim 1, further comprising: a second transmission means for transmitting to a third simulation node for performing a scheduling simulation for the ≦ i ≦ p-2) th partial instruction sequence. Simulation system. The comparison verification unit in the second simulation node compares the state of the instruction scheduling mechanism transmitted by the transmission unit with the state of the instruction scheduling mechanism stored by the storage unit, and a mismatch has occurred. In case,
The second simulation node replaces the state of the instruction scheduling mechanism with the state of the instruction scheduling mechanism transmitted by the transmission means, and then extends to the last instruction of the (i + 1) th partial instruction sequence. The parallel simulation system for a microprocessor according to claim 1, further comprising third subsequent simulation means for performing scheduling simulation again up to the predetermined number of subsequent instruction sequences . An instruction in which all instruction sequences of a simulation target system are subjected to instruction simulation in advance, and an event in which an instruction input to the instruction scheduling mechanism is delayed at that time is set as a candidate for a division point. 4. A parallel simulation system for the microprocessor according to any one of 3 above.

Images