JPH11202839A - Video dislay device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To automatically adjust the amplitude and position of a display image in a display device in which pixels are arrayed in dot matrix. SOLUTION: This video display device is equipped with a PLL(phaselocked loop) circuit 2 which generates a sampling clock, an A/D(analog-to-digital) converter 1 which generates video data by sampling an input video signal, a comparing circuit 9 which outputs a video area signal showing the presence of video information, a counter 11 which counts sampling clocks in the video area signal output period, and a control circuit 8 which performs frequency control over the PLL circuit 2 so that the number of horizontal pixels of the video data output matches the number of horizontal pixels of a liquid crystal panel 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a video display device, and more particularly, to a video display device using a display device in which pixels are arranged in a dot matrix.

[0002]

2. Description of the Related Art Conventionally, in a video display device using a display device such as a liquid crystal panel in which pixels are arranged in a dot matrix, when the resolution of an input video signal does not match the number of pixels of the display device to be used. Or, even if the resolution of the input signal and the number of pixels of the display device are the same, when selecting and using multiple signal sources, the user must adjust the horizontal amplitude, the horizontal position, the vertical amplitude, and the vertical position. I had to do it. Also, in the case of a multi-scan video display device that displays various video signals, various data such as a division ratio and a vertical enlargement ratio for each signal suitable for various video signals are created in advance, It was necessary to preset the display device.

FIG. 5 is a block diagram showing an example of the electrical configuration of a conventional video display device, showing an example of a video display device using a liquid crystal panel in which pixels are arranged in a dot matrix as a display device. I have. Hereinafter, referring to FIG.
A conventional video display device will be described. The video signal a input to the device is converted into an A / D (analog / digital) converter 31.
Is converted into video data composed of digital signals. At this time, a sampling clock for sampling the input signal in the A / D converter 31 is supplied to the display control circuit 32 by a built-in PLL (phase locked loop).
p) The circuit is created based on the input horizontal synchronization signal a and the vertical synchronization signal c.

The video data generated by the A / D converter 31 is subjected to signal processing such as VT correction, polarity inversion, level shift, and multi-phase expansion processing in a video signal processing circuit 33, thereby obtaining a liquid crystal panel. The video data is converted into video data suitable for supply to the. Here, the VT correction is a correction corresponding to the non-linearity between the input voltage and the light transmittance in the liquid crystal panel. The polarity inversion is a process of periodically (eg, for each field) inverting the polarity of the applied voltage in order to prevent a failure in the liquid crystal element when a voltage of the same polarity is applied to the liquid crystal element for a long time. . The level shift is performed to match an output level (for example, 0 to 5 V) of an A / D converter for digitizing a video signal with an optimum input voltage (typically, about 1 to 11 V) in a liquid crystal panel.
This refers to amplitude level compensation processing. In a multi-phase expansion process, a high-resolution liquid crystal panel has a high-speed drive signal. However, in order to compensate for a shortage of video data writing time to the liquid crystal elements, the liquid crystal elements are divided into groups and multi-phase expansion processing is performed. This refers to a process driven by the converted video data.

In the apparatus shown in FIG. 5, a timing signal for actually displaying video data on the liquid crystal panel 34 is created by a liquid crystal panel drive circuit 35. In this case, the user controls the liquid crystal panel drive circuit 35 and the video signal processing circuit 33 via a microcomputer 36 and a remote controller (not shown), a personal computer, or the like. That is, the user operates and changes the timing signal for determining the video display position, the sampling clock frequency of the A / D converter 11 for determining the size of the image in the horizontal direction, and the like. The video data is set so as to be displayed at an appropriate position and size within the screen of the liquid crystal panel 34. In addition, in the case of a multi-scan video display device that displays a plurality of video signals of different resolutions on one video display device, the user not only adjusts the display position while viewing the display screen, but also performs A / D The operation of changing the setting conditions of the plurality of display parameters including the sampling clock frequency of the converter 31 is performed while checking the screen display, so that an optimal display state is obtained.

A technique similar to the above-mentioned conventional technique is disclosed in Japanese Patent Application Laid-Open No. 7-219486.
According to the technique described in the above publication, a liquid crystal display device that samples and outputs a video signal output from a personal computer or the like is provided with an A / D converter, and the input video signal is sampled and the video data is formed of a digital signal. A synchronous reproduction / timing generation circuit, which generates a signal indicating a non-display period of sampling and a screen based on a synchronization signal separated from a video signal, and generates a signal indicating the non-display period according to a control signal. The timing can be changed, a comparison circuit is provided, and it is determined whether or not the video signal is at a signal level equal to or higher than a certain level. When the determination signal indicating that the above is present in the non-display period of the screen, the position of the determination signal The shift is detected, the detection signal is supplied to the synchronous reproduction / timing generation circuit as the above-mentioned control signal, and a video signal processing circuit is provided. The video signal from the A / D conversion circuit is processed, The data is supplied to the liquid crystal panel as video data suitable for display, and a liquid crystal drive circuit is provided, and a timing signal for driving the liquid crystal panel is generated using a signal from the synchronous reproduction / timing generation circuit.

[0007]

However, in the above-mentioned conventional technique, when the number of pixels constituting a display area in a video signal is different due to a difference in hardware or software to be used, one video signal is required. When displaying video data of different number of pixels by the display device, in order to display the input video data on the entire screen of the display device, various kinds of horizontal amplitude adjustment, horizontal position adjustment, vertical amplitude adjustment, vertical position adjustment, etc. The adjustment has to be performed by the user, for example, using a remote controller while directly looking at the display screen, and considerable preparation work is required until the required display state is achieved. In particular, in the case of a multi-scan type video display device for displaying different types of video signals, it is necessary to set various parameters for such adjustment for each video signal to be connected. was there.

Further, in the case of the technique described in the above-mentioned publication, the purpose is to automatically adjust the display position to the optimum position. For this purpose, the total number of horizontal pixels of the input signal must be known. However, in the video signals of existing various systems, the total number of horizontal pixels is not always uniform even if the horizontal synchronization frequency and the vertical synchronization frequency are similar. Therefore, the automatic adjustment of the display position which can be performed by the technique described in this publication is limited.
Also in this case, the horizontal amplitude adjustment and the vertical amplitude adjustment are
Since the automatic adjustment is not performed automatically, there is a problem that the multi-scan video display device cannot perform completely automatic adjustment.

The present invention has been made in view of the above circumstances, and is intended for use when the resolution of an input video signal does not match the resolution of a display device, or when a plurality of signal sources are connected and used. It is another object of the present invention to provide a video display device capable of performing such an adjustment automatically.

[0010]

According to one aspect of the present invention, there is provided a video display device for displaying video data using a display device in which pixels are arranged in a dot matrix. A clock generating means for generating a sampling clock, a sampling means for sampling an input video signal by the sampling clock to generate the video data, and a video indicating the presence of video information when the level of the video data is higher than a reference value. Comparing means for outputting an area signal; clock counting means for counting the number of sampling clocks during the video area signal output period; and changing according to the difference between the count value of the number of sampling clocks and the number of pixels in the horizontal direction of the display device. The frequency control for the clock generating means is performed by the signal of the dividing ratio to be changed. By, and characterized in that it comprises a horizontal amplitude control means for controlling so that the number of pixels in the horizontal direction of the number of pixels in the horizontal direction and the display device in the image data output match.

According to a second aspect of the present invention, there is provided the video display device according to the first aspect, wherein the clock generating means generates the sampling clock having a frequency which varies according to a control voltage; Frequency dividing means for dividing the sampling clock in accordance with the signal of the frequency dividing ratio from the control means to generate a frequency dividing pulse; and comparing the phase of the frequency dividing pulse with the horizontal synchronizing pulse of the input video signal. A phase comparing means for generating the control voltage that changes according to the phase difference.

According to a third aspect of the present invention, there is provided the video display device according to the first or second aspect, wherein the display device is provided with a horizontal driving means for controlling driving of each pixel in the horizontal direction in the display device. Horizontal drive timing control means for controlling the output timing of the drive timing signal corresponding to the first pixel in the device to coincide with the output timing of the video data at the beginning of the output period of the video area signal. Features.

According to a fourth aspect of the present invention, there is provided a video display device for displaying video data using a display device in which pixels are arranged in a dot matrix. Video signal processing means for increasing and decreasing the number of lines and outputting; line number counting means for counting the number of scanning lines in the video data output; and a difference between the count value of the number of lines and the number of vertical lines of the display device. Vertical amplitude control means for controlling the number of scanning lines in the video data output to be equal to the number of lines in the vertical direction of the display device by generating a signal of the enlargement / reduction ratio that changes in response to the signal. It is characterized by becoming.

According to a fifth aspect of the present invention, there is provided the video display device according to the fourth aspect, wherein a vertical driving means for controlling driving of each vertical line in the display device is provided. Vertical drive timing control means for controlling the output timing of the drive timing signal corresponding to the first line to coincide with the output timing of the first line in the video data from the video signal processing means is provided. I have.

[0015] The invention according to claim 6 is based on claim 1,
The video display device according to 2, 3, 4, or 5, wherein the display device is formed of a liquid crystal panel.

[0016]

According to the structure of the first aspect of the present invention, the horizontal amplitude control means controls the frequency division ratio in the clock generation means to change the frequency of the sampling clock for sampling the input video signal, thereby obtaining the video area signal. Since the number of sampling clocks in the period is controlled to match the number of pixels in the horizontal direction of the display device, the number of pixels in the horizontal direction based on the video data is automatically adjusted so as to match the number of pixels in the horizontal direction of the display device. You. Also, at this time, the horizontal drive means for the display device is controlled so that the drive timing of the first pixel of the display device and the output timing of the first video data of the video area signal coincide with each other. Is automatically adjusted so that the horizontal image position coincides with the horizontal display position of the display device.

Further, in the configuration of the invention according to claim 4, the vertical amplitude control means controls the number of scanning lines of the video data according to the difference between the number of scanning lines in the video data output and the number of vertical lines of the display device. The number of scanning lines based on the video data is automatically adjusted so as to match the number of lines in the vertical direction of the display device. Also, at this time, since the driving timing of the first line of the display device is controlled by the vertical driving means for the display device so as to match the output timing of the first line of the video data,
The vertical image position based on the video data is automatically adjusted so as to match the vertical display position of the display device. Therefore, according to the configuration of the present invention, the horizontal and / or vertical size and position of the image of the display device based on the input video data are not adjusted, and the horizontal and / or vertical display areas of the display device are not adjusted. Will match.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. The description will be made specifically using an embodiment. FIG. 1 is a block diagram showing an electric configuration of a video display device according to an embodiment of the present invention.
FIG. 3 is a block diagram illustrating an example of an electrical configuration of a PLL circuit in the device, FIG. 3 is a diagram illustrating an operation flowchart of automatic amplitude / position adjustment in the device, and FIG. 4 is a diagram illustrating an operation timing chart in the device. is there. As shown in FIG. 1, an image display device of this example has an A / D converter 1.
, A PLL circuit 2, a synchronization separation circuit 3, a timing control circuit 4, a video signal processing circuit 5, a liquid crystal panel 6,
Liquid crystal panel drive circuit 7, control circuit 8, comparison circuit 9
, A reference value setting circuit 10, a counter 11, and a counter 12.

The A / D converter 1 converts the video signal A into video data composed of a digital signal in accordance with the sampling clock supplied from the PLL circuit 2. The PLL circuit 2 generates a sampling clock for the A / D converter 1 in phase with the input horizontal synchronization signal B. The synchronization separation circuit 3 extracts a synchronization signal for each unit from the input horizontal synchronization signal B and vertical synchronization signal C. The timing control circuit 4 generates a timing signal for operating each part of the device at a required timing. Video signal processing circuit 5
Performs the same VT correction, polarity reversal, level shift, and multi-phase expansion processing on the video data from the A / D converter 1 as before, and performs processing for enlarging and reducing the image display size. Output to the liquid crystal panel 6. The liquid crystal panel 6 is composed of, for example, a TFT (thin film transistor) active matrix liquid crystal panel,
An image is displayed by an input from the video signal processing circuit 5.

The liquid crystal panel drive circuit 7 receives the signal from the liquid crystal panel 4 based on the timing signal from the timing control circuit 4.
Drive timing signals for driving each pixel in the horizontal and vertical directions. The control circuit 8 controls the entire operation of the video display device and controls the PLL circuit 2 to change the frequency of the sampling clock, thereby realizing enlargement and reduction of the horizontal image display size. Then, the video signal processing circuit 5 is controlled to change the enlargement / reduction ratio, thereby realizing enlargement / reduction of the image display size in the vertical direction.

The comparison circuit 9 compares the level of the video data from the A / D converter 1 with the reference value supplied from the reference value setting circuit 10 and, depending on the result of the comparison, the high level or the low level. Is output to the counter 11. The counter 11 is enabled when the output of the comparison circuit 9 is at a high level, counts the number of sampling clocks from the PLL circuit 2, and outputs the counted number to the control circuit 8.
The counter 12 counts the number of lines of video data in the output of the video signal processing circuit 5 and outputs it to the control circuit 8.

Further, as shown in FIG. 2, the PLL circuit 2 comprises a VCO (voltage controlled oscillator) 21, a counter 22, and a decoder 23.
, A phase comparator 24, and a low pass filter (LPF) 25. VCO
21 generates a sampling clock having a frequency that changes according to the control voltage. The counter 22 counts up the output signal of the VCO 21 and divides the frequency by a fixed frequency division ratio. The decoder 23 converts the frequency of the output of the counter 22 into
The frequency division is performed according to the signal of the frequency division ratio from the control circuit 8. The phase comparator 24 compares the phase of the output signal of the decoder 13 with the horizontal synchronization pulse Hsync separated from the horizontal synchronization signal B in the synchronization separation circuit 3 and outputs a signal whose magnitude changes according to the phase difference. . The LPF 25 includes a phase comparator 24
Is band-limited to generate a control voltage for the VCO 21.

Next, the operation of the video display device of this embodiment will be described with reference to FIGS. In the following, the number of pixels of the liquid crystal panel 6 is, for example, 800 dots horizontal × 600 pixels vertical.
Automatic adjustment of the horizontal and vertical amplitudes and positions in a display image when a video signal having an arbitrary number of pixels is displayed on the liquid crystal panel in the case of a dot will be described. First, the automatic adjustment of the amplitude and the position in the horizontal direction will be described according to the flow shown in FIG. Adjustment of the horizontal amplitude is performed by the horizontal amplitude control function of the control circuit 8. First, the control circuit 8 performs an input signal discrimination for estimating what the signal is from the video signal A input to the video display device, for example, from the frequencies of the horizontal synchronization signal B and the vertical synchronization signal C. (Step S1), and sets the frequency division ratio of the PLL circuit 2 which can be determined to be suitable for this signal (step S1).
2). The division ratio in this case indicates a value obtained by dividing the sampling clock frequency of the A / D converter 1 by the horizontal synchronization frequency.

The PLL circuit 2 generates a sampling clock phase-synchronized with the horizontal synchronizing signal B. In this case, the sampling clock frequency changes according to the frequency division ratio set by the control circuit 8. A / A is sampled by the sampling clock with the division ratio set first.
The amplitude of the digital video data of the D converter 1 is compared with the reference value supplied from the reference value setting circuit 10 by the comparison circuit 9 (step S3). For example, when the reference value supplied from the reference value setting circuit 10 is “10HEX” (a value corresponding to the black level of the screen), if the amplitude of the digital data from the A / D converter 1 is larger than “10HEX”, By generating a high-level output signal from the comparison circuit 9, it is determined that the area is an area where video information exists (hereinafter, referred to as a video area) (step S4). The counter 11 is enabled corresponding to the image area,
The number of sampling clocks input to the A / D converter 1 in the video area is counted (step S5). FIG. 4 illustrates such counting of the number of sampling clocks in the video area.

The control circuit 8 determines whether the frequency division ratio has increased or decreased based on the count value of the counter 11 (step S).
6). The count value 800 of the counter 11 is
If the counter 11 is configured to correspond to a normal image horizontal size on the liquid crystal panel 6 of 0 dots, and if the count value of the counter 11 is smaller than 800, the pixel number of the liquid crystal panel 6 is 800 pixels wide. Since there is not enough data in the area, it is necessary to increase the horizontal amplitude. Therefore, the frequency division ratio of the PLL circuit 2 set by the control circuit 8 is increased (step S7), the sampling clock frequency is increased, and the number of data in the video area is increased. Conversely, if the count value is greater than 800,
By reducing the frequency division ratio of the PLL circuit 2 (step S8),
The number of data in the video area is reduced by lowering the sampling clock frequency. By repeatedly performing the processing including the cycle of the division ratio setting, the comparison of the horizontal amplitude, and the counting of the number of sampling clocks, when the count value of the counter 11 becomes exactly 800, the number of pixels in the horizontal direction in the video data becomes It matches the number of pixels in the horizontal direction of the display device.

Thereafter, the horizontal display position is adjusted so that the image display range matches the display area of the liquid crystal panel 6 (step S9). The horizontal display position is adjusted by adjusting the drive timing signal for each pixel in the horizontal direction of the liquid crystal panel 6 so that the output timing of the first video data in the output period of the video area signal corresponds to the first pixel of the liquid crystal panel 6. Can be achieved by changing the output timing of the horizontal drive timing signal from the liquid crystal panel drive circuit 7. More specifically, a horizontal drive unit (not shown) that performs drive control for each pixel in the horizontal direction of the liquid crystal panel 6 in the liquid crystal panel drive circuit 7 is controlled by a horizontal drive timing control in the timing control circuit 4. Part (not shown)
However, this is realized by performing control so that the output timing of the drive timing signal corresponding to the first pixel in the liquid crystal panel 6 matches the output timing of the video data at the beginning of the output period of the video area signal.

Next, according to the flow shown in FIG.
The automatic adjustment of the amplitude and the position in the vertical direction will be described. In this example, a case will be described in which amplitude adjustment in the vertical direction is performed using the enlargement and reduction functions. Adjustment of the amplitude in the vertical direction is performed by the vertical amplitude control function of the control circuit 8. First, the control circuit 8 determines the input signal of the video signal input to the video display device in the same manner as in the horizontal direction (step P1), and enlarges or reduces in the vertical direction that can be determined to be suitable for this signal. The rate is set in the video signal processing circuit 5 (step P2). The enlargement / reduction ratio in this case is a value obtained by dividing the number of vertical lines of the liquid crystal panel 6 by the number of scanning lines in the video data output of the video signal processing circuit 5.

The number of video data output lines of the video signal processing circuit 5 based on the initially set enlargement / reduction ratio is counted by the counter 12 (step P3). The control circuit 8 determines whether the enlargement / reduction ratio has been increased or decreased based on the count value of the counter 12 (step P4). When the number of lines counted by the counter 12 is smaller than the number of lines 600 of the liquid crystal panel 6 in the vertical direction, the control circuit 8 controls the video signal processing circuit 5
Is instructed to increase the enlargement / reduction ratio (step P5), and when the number of lines counted by the counter 12 is larger than the number of lines 600 in the vertical direction of the liquid crystal panel 6, the control circuit 8 sends the video signal An instruction to reduce the enlargement / reduction ratio is issued to the processing circuit 5 (step P6).

The video signal processing circuit 5 controls the increase or decrease of the number of lines for video data input in accordance with an instruction to increase or decrease the enlargement / reduction ratio. In the video signal processing circuit 5 in this case, the process of increasing / decreasing the number of lines is performed, for example, when increasing the number of lines, by interpolating lines or repeating the same lines in an averagely dispersed manner over the entire scanning lines. To reduce the number, thin out the line,
This can be realized by performing the dispersion on the entire scanning line on average. By repeating such processing of setting the enlargement / reduction ratio and increasing / decreasing the number of lines, the counter 12
Is just 600, the number of scanning lines of the video data output from the video signal processing circuit 5 matches the number of vertical lines of the display device.

Thereafter, the vertical display position is adjusted so that the image display range matches the display area of the liquid crystal panel 6 (step P7). The vertical display position is adjusted so that the first line of the output of the video signal processing circuit 5 corresponds to the first line of the liquid crystal panel 6.
May be generated by changing the output timing of the drive timing signal from the liquid crystal panel drive circuit 7. Specifically, a vertical drive unit (not shown) that performs drive control for each vertical line of the liquid crystal panel 6 in the liquid crystal panel drive circuit 7 is controlled by a vertical drive timing control in the timing control circuit 4. Part (not shown)
This is realized by controlling the output timing of the drive timing signal corresponding to the first line on the liquid crystal panel 6 so as to match the output timing of the first line in the video data output from the video signal processing circuit 5.

Although the embodiment of the present invention has been described in detail with reference to the drawings, the specific structure is not limited to this embodiment, and there are design changes and the like without departing from the gist of the present invention. Even this is included in the present invention. For example, the display device to which the present invention is applied is not limited to a liquid crystal panel, but may be an EL device.
(Electroluminescence) display or plasma display may be used.

The video display device of this example may be entirely or partially of a hardware configuration or a software configuration. A part (for example, the control circuit 8) of the video display device of this example includes a CPU (central processing unit), a ROM
Internal storage such as AM, FDD (flexible disk driver), HDD (hard disk driver), C
It is preferable that the computer is configured by a computer having an external storage device such as a D-ROM driver, an input device such as a keyboard and a mouse, and a display device.
It is preferable that a recording medium such as an FD (flexible disk), an HD (hard disk), or a CD-ROM records a control program for causing a computer to execute the processing of the control circuit 8 described above. The recording medium may be a semiconductor memory or another recording medium. In such a configuration, the control program is read into the computer from the recording medium and controls the operation of the computer. When the control program runs, the computer executes the control circuit 8 described above.
Perform the function of.

When the present invention is applied to a multi-scan video display device that displays a plurality of types of video signals, data serving as a reference for setting the horizontal amplitude, the horizontal position, the vertical amplitude, and the vertical position is defined as: Different types of video signals were input if only representative video signals were created, and in the case of this video signal, a display matching the number of dots in the vertical and horizontal directions of the liquid crystal panel could be performed. In this case, the same processing as in the above embodiment is performed, and the horizontal amplitude,
By automatically setting the horizontal position, the vertical amplitude, and the vertical position, the display can be performed on the same liquid crystal panel. In this way, the designer does not need to create data such as the division ratio and the enlargement / reduction ratio for each signal suitable for each video signal in advance and preset them in the apparatus. By simply creating and setting only reference data for a typical signal, automatic adjustment is possible for other signals, so that the burden on the designer can be reduced.

[0034]

As described above, according to the structure of the first aspect, the number of pixels in the horizontal direction based on the video data can be automatically made to coincide with the number of pixels in the horizontal direction of the display device. The horizontal image position based on the video data can be automatically matched with the horizontal display position of the display device.

According to the fourth aspect of the present invention, the number of scanning lines in the video data can be automatically matched with the number of vertical lines of the display device, and the vertical image position based on the video data can be adjusted. Can be automatically matched with the vertical display position of the display device.

Therefore, even when the pixel configuration of the input video signal does not match the pixel configuration of the display device, or even when the input video signal and the pixel configuration of the display device are the same, a plurality of signal sources are connected and used. In such a case, the user does not need to adjust the horizontal amplitude, the horizontal position, the vertical amplitude, and the vertical position, so that the operation burden on the user can be greatly reduced.

Further, in one display device, an image is displayed corresponding to a plurality of image signals having different pixel configurations.
Even in the case of a multi-scan video display device, even if the data such as the division ratio and the enlargement / reduction ratio for each signal suitable for each video signal is not preset in the device,
Since the amplitude and the position can be automatically adjusted, the design of the apparatus is also facilitated.

[Brief description of the drawings]

FIG. 1 is a block diagram schematically showing an electrical configuration of a video display device according to an embodiment of the present invention.

FIG. 2 is a diagram showing an operation flowchart of automatic amplitude / position adjustment in the apparatus.

FIG. 3 is a diagram showing an operation timing chart in the same device.

FIG. 4 is a diagram showing an example of an electrical configuration of a PLL circuit included in a control circuit of the device.

FIG. 5 is a block diagram showing an example of an electrical configuration of a conventional video display device.

[Explanation of symbols]

Reference Signs List 1 A / D converter (sampling means) 2 PLL circuit (clock generation means) 3 Synchronization separation circuit 4 Timing control circuit (horizontal drive timing control means, vertical drive timing control means) 5 Video signal processing circuit (video signal processing) Means 6 liquid crystal panel (display device) 7 liquid crystal panel drive circuit (horizontal drive means, vertical drive means) 8 control circuit (horizontal amplitude control means, vertical amplitude control means) 9 comparison circuit (comparison means) 10 reference value setting Circuit 11 Counter (clock number counting means) 12 Counter (line number counting means) 21 VCO (oscillating means) 23 Decoder (frequency dividing means) 24 Phase comparator (phase comparing means)

Claims (6)

[Claims] 1. A video display device for displaying video data as an image using a display device in which pixels are arranged in a dot matrix, comprising: a clock generation means for generating a sampling clock; and an input video signal sampled by the sampling clock. Sampling means for generating the video data, a comparing means for outputting a video area signal indicating the presence of video information when the level of the video data is greater than a reference value, counting the number of sampling clocks in the video area signal output period Clock counting means for controlling the frequency of the clock generating means by a signal having a frequency division ratio which varies according to a difference between the count value of the number of sampling clocks and the number of horizontal pixels of the display device. Number of pixels in horizontal direction in data output and previous Image display device characterized by comprising a horizontal amplitude control means for controlling so that the number of pixels in the horizontal direction of the display device coincide. 2. The clock generating means includes: an oscillating means for generating the sampling clock having a frequency that varies according to a control voltage; and an oscillator for generating the sampling clock according to a signal of the frequency division ratio from the horizontal amplitude control means. Frequency dividing means for generating a frequency-divided pulse by dividing the frequency; phase comparing means for comparing the phase of the frequency-divided pulse with the horizontal synchronizing pulse of the input video signal to generate the control voltage that changes according to the phase difference; The image display device according to claim 2, comprising: 3. An output timing of a drive timing signal corresponding to a first pixel in the display device is set to a horizontal drive unit for performing drive control on each pixel in a horizontal direction in the display device. 3. The video display device according to claim 1, further comprising a horizontal drive timing control unit that controls the output timing of the video data to coincide with the output timing of the video data at the beginning of the output period. 4. A video display device for displaying video data using a display device in which pixels are arranged in a dot matrix, wherein the number of scanning lines in the video data is increased or decreased in accordance with a signal of an enlargement / reduction ratio and output. A video signal processing unit, a line number counting unit for counting the number of scanning lines in the video data output, and a line number changing unit that changes according to a difference between the count value of the line number and the number of vertical lines of the display device. Vertical amplitude control means for controlling the number of scanning lines in the video data output to be equal to the number of lines in the vertical direction of the display device by generating a signal of an enlargement / reduction ratio. Video display device. 5. An output timing of a drive timing signal corresponding to a first line in the display device, the output timing of the video signal processing means being provided to a vertical drive unit for performing drive control for each vertical line in the display device. 5. The video display device according to claim 4, further comprising a vertical drive timing control means for controlling the output timing of the first line in the video data from the first line to coincide with the output timing. 6. The video display device according to claim 1, wherein said display device comprises a liquid crystal panel.