JPH07219485A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To automatically adjust the phase of sampling clocks. CONSTITUTION:The data of a part or all of multiple lines of a frame and the data of the same portion of the (n)th frame are compared by a comparing circuit 10 via sampling clocks having a constant phase, whether they nearly coincide with each other or not is judged by a controller 11 for each horizontal scanning line, and the number of scanning lines that they nearly coincide with each other is counted. The above actions are repeated while the sampling phase is changed, and the count numbers and the sampling phases are stored in the second memory 12. The sampling phase having the largest number of scanning lines that the data of the (n)th frame nearly coincide with each other is employed, and this sampling phase is used for the display of the image signal. The phase of the sampling clocks can be automatically set nearly at the center of the picture elements of the image signal, and adequate sampling can be implemented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device for sampling and displaying a video output signal of a personal computer or the like, and more particularly to a liquid crystal display device for automatically adjusting the phase of a sampling clock.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram of a liquid crystal display device for sampling and displaying a video output signal of a conventional personal computer. Here, in this liquid crystal display device, the number of effective pixels is 640
X vertical 480, total 800 horizontal 800 x vertical 525 analog video signals are input.

An analog video signal is supplied to an A / D converter 42 via an input terminal 41. This A / D converter 4
At 2, the analog video signal is converted into a digital video signal at the timing of the sampling clock supplied from the sampling clock generation circuit 46 described later. This digital video signal is sent to the video signal processing circuit 43.
Is supplied to.

In the video signal processing circuit 43, the digital video signal is subjected to gamma correction, polarity inversion and the like. Then, the processed digital video signal is supplied to the liquid crystal panel 44.

A horizontal synchronizing signal HD separated from the analog video signal is supplied to a sampling clock generating circuit 46 and a liquid crystal driving circuit 49 via an input terminal 45.

The video output signal of the personal computer, unlike the normal video signal, is not a completely continuous signal but a signal having a constant level for each pixel. On the other hand, the liquid crystal display device cannot continuously display the signal of one scanning line, and the signal sampled for each pixel is displayed. Therefore, when displaying the video output signal of the personal computer on the liquid crystal display device,
Generally, the pixels of the personal computer and the pixels of the liquid crystal display device are displayed in a ratio of 1: 1 or 1: integer.

In the conventional example described here, the pixels of the personal computer and the pixels of the liquid crystal display device are in one-to-one correspondence, so that the sampling clock generation circuit 46 is used.
Then, based on the horizontal synchronizing signal HD supplied from the input terminal 45, the horizontal total number of pixels is multiplied by the frequency of the horizontal synchronizing signal (800
A sampling clock CK having a frequency of 2 times) is generated.

A horizontal synchronizing signal H is input through the input terminal 45.
D, the clock CK from the sampling clock generation circuit 46, and the vertical synchronizing signal VD from the terminal 48 are supplied to the liquid crystal drive circuit 49, respectively.
In the liquid crystal drive circuit 49, the horizontal synchronizing signal HD and the clock C
A timing signal necessary for driving the liquid crystal is formed based on K and the vertical synchronizing signal VD, and is supplied to the liquid crystal panel 44 as a liquid crystal display element.

In the liquid crystal panel 44, the liquid crystal pixels are driven by the pixel data supplied from the video signal processing circuit 43 in accordance with the timing signal supplied from the liquid crystal drive circuit 49, and an image is displayed.

However, as described above, since the output video signal of the personal computer is a signal having a constant level for each pixel, there is no problem if the sampling phase is near the center of the pixel, but If the phases are shifted and the pixels are switched, the following problems occur.

That is, when sampling the signals to be displayed at the same position on the screen, the sampling clock CK
Due to the influence of the jitter of 1, the pixel at the previous position may be sampled in one frame and the pixel at the later position may be sampled in another frame. When this happens,
The edges of the image will flicker, making it very difficult to see.

For this reason, the sampling clock generation circuit 46 has a built-in circuit for changing the phase of the sampling clock CK, and the phase can be adjusted by operating the sampling clock phase adjustment switch 47. A circuit for changing the phase of the sampling clock CK is, for example, as shown in FIG.

The circuit shown in FIG. 3 is composed of a general PLL circuit, and the horizontal synchronizing signal H is applied to a terminal 461.
D is being supplied. Voltage controlled oscillator (hereinafter referred to as VCO
462, the frequency is 80 of the horizontal synchronizing signal HD.
The clock of 0 times is formed, and the 800 divider circuit 463,
It is supplied to the output terminal 468. In the 800 frequency divider circuit 463, the frequency of the output signal of the VCO 462 is (1/8)
00), and the frequency-divided signal whose frequency is equal to that of the horizontal synchronizing signal HD is obtained and supplied to the phase comparator 464.

The phase comparator 464 compares the phases of the horizontal synchronizing signal HD and the frequency-divided signal supplied from the terminal 461 to obtain a phase error. The obtained phase error signal is supplied to one input terminal of the adder 466. On the other hand, the sampling phase control signal is supplied to the other input terminal of the adder 466 via the terminal 465. This sampling phase control signal is created based on the operation of the sampling clock phase adjustment switch 47 and is used to give an offset to the phase error signal.

The adder 466 adds the phase error signal and the sampling phase control signal, and the added output is supplied to the integrator 467. The integrator 467 integrates the addition output, and the integrated result is the VCO 46.
2 is supplied. In this way, by adding an offset to the phase error signal from the phase comparator 464, the PLL
Change the locked phase of the sampling clock C
The phase of K can be controlled.

In other words, in order to sample the output video signal of the personal computer to form pixel data and display the pixel data as a video without flicker, the phase of the sampling clock is adjusted while the user looks at the displayed screen. The switch 47 had to be adjusted.

[0017]

As described above, in order to display the video output signal of the personal computer as a video without flicker in the conventional liquid crystal display device, the phase of the sampling clock is changed while watching the screen displayed by the user. It had to be adjusted by the adjusting means, which was troublesome. At the same time, there is a problem that a phase adjusting means such as a sampling clock phase adjusting switch is required, and the configuration of the operating means becomes more complicated.

Therefore, the present invention is for eliminating such a problem, and when sampling and displaying the video output signal of the personal computer, the phase of the sampling clock can be automatically adjusted to the optimum state. An object of the present invention is to provide a liquid crystal display device.

[0019]

A liquid crystal display device according to the present invention comprises an A / D conversion means for sampling an input video signal under a sampling clock having a constant phase and converting it into a digital signal. Sampling clock generating means for generating the sampling clock based on a horizontal synchronizing signal separated from a video signal, means for changing the phase of the sampling clock of the sampling clock generating means during phase adjustment of the sampling clock, and the A / D First memory means for storing pixel data of at least a predetermined portion in the first frame sampled by the converting means, and the first frame stored in the first memory means, with respect to the first frame, Pixel data in the second frame after n (n is an integer of 1 or more) frames from the A / D conversion means Comparing the pixel data at a position corresponding to the predetermined portion in the first frame to determine the coincidence for each horizontal scanning line, the first frame and the second frame. A counting unit that counts the number of horizontal scanning lines that coincide with each other when there is a match for each horizontal scanning line with the frame, a count value by the counting unit, and phase information of the sampling clock corresponding to the value. Two
Memory means, means for setting the phase of the sampling clock at the time of image display in the sampling clock generating means based on the count value stored in the second memory means, and digital signal from the A / D conversion means. The video signal processing means for processing the signal and supplying it to the liquid crystal display element as pixel data, the sampling clock from the sampling clock generating means, the horizontal synchronizing signal and the vertical synchronizing signal separated from the video signal, And a liquid crystal driving means for generating a timing signal for driving the display element.

[0020]

According to the invention of the above construction, the pixel data of at least a predetermined portion in the first frame is stored in the first memory means by the sampling clock having a constant phase.
A frame after n frames have elapsed from the first frame is set as a second frame, and pixel data of the same portion of the second frame as the first frame is compared with pixel data of the first frame, Is determined for each horizontal scanning line. Then, the number of scanning lines that substantially match is counted. The above operation is repeated while changing the sampling phase, and this count value and the sampling phase at that time are stored in the second memory means.
Then, the sampling phase having the largest number of scanning lines in which the data after n frames are substantially the same is adopted, and the sampling phase is used for displaying the video signal. As a result, the phase of the sampling clock can be automatically set near the center of the pixel, and appropriate sampling can be executed.

[0021]

EXAMPLES Examples will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.
In this embodiment, a liquid crystal display device for sampling and displaying a video output signal of a personal computer will be described.

An analog video signal of horizontal 640 × vertical 480 for effective pixels and horizontal 800 × vertical 525 for total pixels is input to the liquid crystal display device from a personal computer.

This analog video signal is supplied to the A / D converter 2 via the input terminal 1. This A / D converter 2
Then, the analog video signal is converted into a digital video signal at the timing of the sampling clock CK supplied from the sampling clock generation circuit 7. This digital video signal is supplied to the video signal processing circuit 3.

The sampling clock generating circuit 7 generates a sampling clock CK having a frequency that is a total number of horizontal pixels times (800 times) the frequency of the horizontal synchronizing signal based on the horizontal synchronizing signal HD supplied from the input terminal 5. It is supplied to the A / D converter 2, the video signal processing circuit 3, and the liquid crystal drive circuit 8, respectively.

In the video signal processing circuit 3, a sampling clock generating circuit 7 is applied to the digital video signal.
Processing such as gamma correction and polarity inversion is performed at the timing of the sampling clock CK from. Then, the processed digital video signal is supplied as pixel data to the liquid crystal panel 4 as a liquid crystal display element.

The horizontal synchronizing signal HD separated from the analog video signal is supplied to the sampling clock generating circuit 7 and the liquid crystal driving circuit 8 through the input terminal 5.

The liquid crystal driving circuit 8 receives the horizontal synchronizing signal HD from the input terminal 5 and the sampling clock generating circuit 7
From the input terminal 6 and the vertical synchronizing signal VD from the input terminal 6. The liquid crystal drive circuit 8 forms a timing signal required for driving the liquid crystal based on the horizontal synchronizing signal HD, the sampling clock CK, and the vertical synchronizing signal VD, and supplies the timing signal to the liquid crystal panel 4.

In the liquid crystal panel 4, the liquid crystal pixels are driven using the pixel data supplied from the video signal processing circuit 3 in accordance with the timing signal supplied from the liquid crystal drive circuit 8 to display a video.

A / A required for displaying images
The D converter 2, the video signal processing circuit 3, the liquid crystal panel 4, the sampling clock generating circuit 7 and the liquid crystal driving circuit 8 are the same as those in the conventional example of FIG. In the embodiment of the present invention, in addition to the above configuration, a first memory 9, a comparison circuit 10, a controller 11 and a second memory 12 are provided as means for automatically adjusting (setting) the phase of the sampling clock CK. It is configured. Therefore, the sampling clock adjustment switch of the conventional example (FIG. 2) is deleted.

The output of the A / D converter 2 is input to the first memory 9 and the comparison circuit 10 in addition to the video signal processing circuit 3 as described above.

The controller 11 includes a first memory 9 and a second memory
In addition to the means for controlling writing and reading of the memory 12, the sampling clock generation circuit is used when the adjustment start signal for starting the adjustment of the sampling clock phase is input from the terminal 13 and the phase of the sampling clock is adjusted. 7, a means for generating a sampling phase control signal S to change the phase of the sampling clock CK, and a pixel of a predetermined portion consisting of a plurality of horizontal scanning lines (hereinafter referred to as lines) of the frame written in the first memory 9. When the comparison circuit 10 compares the data with the pixel data corresponding to the predetermined portion after n (n is an integer of 1 or more) frames has passed, the number of coincident lines is counted when there is coincidence in line units. Means and a plurality of second memory 12 storing the count value together with the sampling phase at that time. Based on the data of the sampling phase corresponding to, for example, largest count value among the count values to generate a sampling phase control signal S, after the phase adjustment (when displaying the image), the sampling clock generating circuit 7
And means for adjusting (setting) the phase of the sampling clock CK generated in (1) to the optimum state.

The first memory 9 writes some or all of the signals of a plurality of lines in the input video signal, n
After (n is an integer equal to or greater than 1) frames, it is controlled to read when the same portion of data as the already written data is input.

The comparison circuit 10 compares the data of a part or all of a plurality of lines of a certain frame with the data of the same part n frames thereafter, determines whether they are substantially the same, and the controller 11 Output.

The controller 11 calculates the number of lines in which the data between the n frames are almost the same, and the calculated number of lines is
It is written in the second memory 12 together with the data D of the sampling phase at that time from the liquid crystal drive circuit 8.

At the phase adjustment, the controller 11 performs the above operation (first memory 9, comparison circuit 10 and second memory 1).
The operation 2) is repeated for a certain period of time while changing the sampling phase. That is, at the time of phase adjustment, the controller 11 generates the sampling phase control signal S at the same time as the input of the adjustment start signal from the terminal 13, and the sampling clock generation circuit 7 is controlled by this control signal S, so that n frames elapse. The above operation is repeated by changing the sampling phase for each time, and the data of the sampling phase having the largest number of substantially matched lines is selected from the second memory 12 and the clock phase of the sampling clock generation circuit 7 is controlled to an appropriate state ( Set) and use it to display the video signal. If the number of matching lines is more than a certain value, it can be determined that flicker does not occur in that sampling phase, so set it to an intermediate value in the sampling phase where the number of matching lines is more than a certain value. May be set (without setting the maximum value).

During this adjustment, the sampling phase is moved, so a normal screen is not output. Further, when the input video signal is moving, the moving part does not substantially match in n frames, so it is necessary to input a video signal that is as stationary as possible. Therefore, adjustment is performed by the adjustment start signal input from the terminal 13 after inputting a still or almost still image signal for adjustment, and the adjustment is not performed during normal use (during image display). .

The operation will be described below.

When adjusting the sampling phase, a still image signal for adjustment is input to the input terminal 1 as an input video signal, and then an adjustment start signal is input to the input terminal 13. This adjustment start signal is generated by instructing the adjustment start with an operating means (not shown). When the adjustment start signal is input, the controller 11 is set to a mode for adjusting the phase of the sampling clock CK for a fixed time, and the first
The write control of the memory 9, the write and read control of the second memory 12, and the control of the sampling clock phase for the sampling clock generation circuit 7 are performed according to a predetermined procedure.

That is, the analog video signal of the still image is A / D
The converter 2 converts the sampling clock CK into a digital video signal while keeping the phase of the sampling clock CK at a certain value.
The digital video signal is supplied to the video signal processing circuit 3, the first memory 9 and the comparison circuit 10, respectively.

Under the control of the controller 11, some or all of the plurality of lines of the input video signal are written in the first memory 9.

In the comparison circuit 10, the data in the first memory 9 is compared with the data in the same portion in the frame n frames after that. Then, it is determined whether or not they are substantially the same, and the determination result for each line is output to the controller 11.

The controller 11 counts the number of lines determined to match among the plurality of lines, and writes this number of lines in the second memory 12 together with the sampling phase at that time. The above operation is repeated while changing the sampling phase, and the second memory 12
Write in. After a lapse of a fixed time from the input of the adjustment start signal, the controller 11 selects, from the second memory 12, the data of the sampling phase corresponding to the most matching number of lines, and the sampling phase control signal based on the data. S is generated and the sampling clock generating circuit 7 is controlled to set the phase of the sampling clock CK to an appropriate state. Note that, as described above, when the number of substantially matched lines is equal to or greater than a certain value, it can be determined that flicker has not occurred in that sampling phase, and therefore, when the number of matched lines is equal to or greater than a certain value. It may be set to an intermediate value.

On the other hand, during normal video display, the analog input video signal is sampled by the A / D converter 2 in accordance with the sampling clock CK and its phase set by the controller 11 at the time of adjusting the sampling phase, and converted into a digital video signal. To be converted. The video signal processing circuit 3 performs video processing such as gamma correction according to the set sampling clock CK and its phase,
It is supplied to the liquid crystal panel 4 as pixel data. Further, in the liquid crystal drive circuit 8, the set sampling clock CK
Then, a liquid crystal driving timing signal is created using the horizontal synchronizing signal HD and the vertical synchronizing signal VD separated from the input video signal and is supplied to the liquid crystal panel 4 to display the pixel data as a video.

[0044]

As described above, according to the present invention, it is not necessary for the user to adjust the sampling phase while looking at the screen, and it is possible to easily and automatically adjust the optimum sampling phase. Further, the phase adjusting means can be dispensed with, and the construction of the operating means can be further simplified.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional liquid crystal display device.

3 is a block diagram showing an example of a sampling phase adjustment circuit in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Video signal input terminal 2 ... A / D converter 3 ... Video signal processing circuit 4 ... Liquid crystal panel 5 ... Horizontal sync signal input terminal 6 ... Vertical sync signal input terminal 7 ... Sampling clock generation circuit 8 ... Liquid crystal drive Circuit 9 ... First memory 10 ... Comparison circuit 11 ... Controller 12 ... Second memory 13 ... Adjustment start signal input terminal

Claims (1)

[Claims] 1. An A / D conversion means for sampling an input video signal under a sampling clock having a constant phase and converting it into a digital signal, and the horizontal sync signal separated from the video signal, based on the horizontal synchronizing signal. Sampling clock generating means for generating a sampling clock; means for changing the phase of the sampling clock of the sampling clock generating means during phase adjustment of the sampling clock; and within the first frame sampled by the A / D converting means. A first memory means for storing pixel data of at least a predetermined portion of the first frame, and n (n is 1) from the A / D conversion means for the first frame stored in the first memory means. (Integer number greater than or equal to) The pixel data in the second frame after the frame and the predetermined number in the first frame. Comparing means for comparing the pixel data at the position corresponding to the portion to determine the coincidence for each horizontal scanning line; and the coincidence for each horizontal scanning line between the first frame and the second frame. Counting means for counting the number of horizontal scanning lines coincident at a certain time, second count means for storing the count value by this count means, and phase information of the sampling clock corresponding to the count value, and this second memory means Based on the stored count value,
Means for setting the phase of the sampling clock at the time of displaying an image in the sampling clock generating means, video signal processing means for processing the digital signal from the A / D conversion means and supplying it as pixel data to the liquid crystal display element, And a liquid crystal driving means for generating a timing signal for driving the liquid crystal display element by using a sampling clock from the sampling clock generating means and a horizontal synchronizing signal and a vertical synchronizing signal separated from the video signal. Characteristic liquid crystal display device.