JPH11184798A - Data communication equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the increase of direct memory access(DMA) processing load and the reduction of DMA transfer performance by determining the address of a reception area on a buffer memory through an address translating means. SOLUTION: A bus arbitrating means 17 performs the arbitrating processing of access requests from respective master devices, applies the permission of access to each access request in prescribed order and reports a service class showing which master device gets the permission of access to an address translating means 20. When the service class is reported from the bus arbitrating means 18, the address translating means 20 compares an address value on an address bus with a reception port address 31 fixedly allocated in advance through a comparator circuit 32 and when they are not coincident, an address value outputted by an address generating circuit 39 or when they are coincident, an address value outputted by an address generating circuit 39 is selected by a selector circuit 40 and outputted to a buffer memory 19.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data communication apparatus mutually connected via a LAN, and more particularly to a data communication apparatus for transferring data transmitted and received between memories in the data communication apparatus.

[0002]

2. Description of the Related Art When performing data transmission between data communication devices connected to a transmission line, each data communication device temporarily stores transmission data in a buffer memory in the data communication device and assigns an access right to the transmission line. At the time when it is obtained, it is sent to the transmission line and constantly monitors the data being transmitted on the transmission line,
When data addressed to the own data communication device is detected, the data is stored in the reception area of the buffer memory. The reception data stored in the reception area is transmitted to a direct memory access controller (hereinafter, DM) in the data communication device.
(Abbreviated as AC) from the buffer memory to the host memory in the computer.

In a conventional data communication apparatus, when data is transferred between a buffer memory and a host memory, an MPU reads a data length stored in received data in the buffer memory, and reads the data length and a buffer memory of a transfer source. The DMAC is started after setting the received data start address and the start address of the transfer destination reception area in the host memory. In addition, the MPU calculates the head address of the buffer memory in which the next received data is stored from the value of the data length, and uses it as a set value when the next DMAC is started.

[0004] The activated DMAC reads the received data from the buffer memory and writes the data to the host memory. The read and write operations are repeated for the data length.

[0005]

However, in the known data communication device, the MPU calculates the data length and the start address of the transfer data, and every time a DMA transfer is performed, the transfer source / destination address and the transfer data length are calculated. D after setting
It is necessary to start up the MAC, which causes problems such as an increase in the DMA processing load of the MPU and a decrease in data transfer performance.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate this problem and increase the DMA processing load of the MPU and the DMA transfer in data transfer between a buffer memory and a host memory.
An object of the present invention is to provide a data transfer method capable of preventing a decrease in transfer performance.

[0007]

Means for Solving the Problems Communication control means, MPU,
DMAC, buffer memory for storing transmission / reception data, M
In a data communication apparatus provided with a bus arbitration means for giving an access permission in response to an access request output from a PU and a DMAC, the bus arbitration means outputs the type of the device to which the access permission has been given, and responds to the type of the device. Address conversion means for generating an address when accessing the buffer memory. At the beginning of the data stored in the buffer memory, the received data length is stored.
At the time of startup, after setting the reception data length, the system is started to access a predetermined address.

[0008]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 2 shows a configuration of a transmission system to which the present invention is applied and a configuration of a data communication device. In the present transmission system, a plurality of data communication devices 5 to 7 are mutually connected via a transmission line 1, and computers 2 to 4 are connected to the data communication devices 5 to 7, respectively. Each data communication device has an MPU
14, DMAC 15, bus arbitration means 17, communication control means 18,
A buffer memory 19 and address conversion means 20 are provided. Each computer has a CPU 11 and a host memory 1
2 are provided, and the data communication device and the computer are connected by a system bus 13. Here, when data is transmitted between computers, the CPU 11 writes transmission data in a transmission area on the host memory 12 and the DMAC 15 in the data communication device.
Then, the transmission data is read from the host memory 12 and transferred to the buffer memory 19, and is transmitted from the buffer memory 19 to the transmission line 1 by the communication control unit 18. The data on the transmission path 1 is determined by the communication control means 18 to determine whether it is addressed to the own computer or not. It is transferred to 12 reception areas.

Next, the data received from the transmission line 1 is stored in the buffer memory 19 and the host memory 1 with reference to FIGS.
Next, an address conversion method in the case of transferring data to C.2 will be described.

The data addressed to the own computer received from the transmission line 1 is transferred to the buffer memory 19 by the communication control means 18. When transferring received data to the buffer memory 19, the communication control means 18 accesses a receiving port assigned to a fixed address on the address map. Each time the communication control unit 18 accesses the reception port, the address conversion unit 20 outputs data to the buffer memory 19 having the address value sequentially incremented from the head address of the reception area. Received data is written sequentially from the address.

Next, the received data that has been transferred to the buffer memory 19 is transferred to the host memory 12 by the DMAC 15. The DMAC 15 needs to set the transfer data length and the start address of the transfer source / destination. Accesses the reception port to read the data length stored in the specific position of the reception data. At the head of each reception data in the reception area, the data length of the received data is stored as shown in FIG. The address translation means 20
Each time the MPU 14 accesses the receiving port,
The head address value of each reception data in the reception area is sequentially output to the buffer memory 19. This allows MPU1
For 4, the buffer memory 19 returns the data length of each received data. After setting this value as the transfer data length for the DMAC 15, the MPU 14 activates the DMAC 15.

The DMAC 15 started from the MPU 14 accesses the receiving port. The address translation means 20
Each time the DMAC 15 accesses a predetermined reception port, an address value sequentially incremented from the head address of the reception area is output to the buffer memory 19, and as a result, the reception data is sequentially read from the head address of the reception data. . The DMAC 15 writes the data read via the address conversion means 20 to the host memory 12 via the system bus 13, repeats this operation for the data length, and transfers the received data from the buffer memory 19 to the host memory 12.

Next, while transferring data received from the transmission line 1 by the communication control means 18 to the reception area of the buffer memory 19, the address conversion when reaching the final address of the reception area will be described with reference to FIGS. This will be described with reference to FIG.

The address conversion means 20 is a communication control means 1
8 is accessing the receiving port, while buffer memory 1
When the address value output to the buffer memory 9 reaches the last address of the reception area, the address value output to the buffer memory 19 from the next time is returned to the head of the reception area, and the address value sequentially incremented for each access again is stored in the buffer memory 19. Output to Here, as shown in FIGS. 5 and 6, the front part and the rear part of the reception data 3 are divided and stored.
Similarly, at the time of access from the DMAC 15, the address value output to the buffer memory 19 is returned to the head of the reception area.

The address conversion means 20 returns to the head of the reception area in the next access when the MPU 14 accesses the reception port and reads the data length of the reception data 3 and stores the head address value of the next reception data 4 in the buffer memory. 19 is output.

Next, the configuration of the data communication device will be described in detail with reference to FIG.

Communication control means 18, MPU 14, and DMAC
When accessing the buffer memory 19 (hereinafter, the communication control means 18, the MPU 14, and the DMAC 15 are referred to as master devices), the access request 15 outputs an access request to the bus arbitration means 17. The bus arbitration unit 17 performs an arbitration process for an access request from each master device, gives access permission to each access request in a predetermined order,
The service type indicating which of the master devices has been granted access permission is notified to the address conversion means 20.

The master device to which the access permission is given outputs an address indicating the receiving port to be accessed on the address bus, and if the master device to which the access permission is given is the communication control means 18, the data to be written into the buffer memory 19 Output the value on the data bus.

The address conversion means 20 has registers for storing the reception port address 31 and the reception area start address 33 / reception area end address 34, respectively, and the buffer memory 19 when each master device accesses the reception port. MPU access address 36 / DMAC access address 37 / communication control means access address 3 used to determine output address
5, a register for storing the received data length 38 in the address conversion means 20 when the MPU 14 reads the data length stored at the head of the received data, and a notification from the bus arbitration means 17. An address generating circuit 39 for selecting an address to be output to the buffer memory 19 and calculating an address value at the time of the next access according to the type of service provided. Predetermined values are set in advance in the registers for storing the reception port address 31, the reception area start address 33 / the reception area end address 34, and store the MPU access address 36, the DMAC access address 37, and the communication control means access address 35. The start address of the reception area is set in each register as an initial value.

The address translating means 20 comprises a bus arbitrating means 1
When the service type is notified from 7, the comparison circuit 32 compares the address value on the address bus with the reception port address 31 fixedly assigned in advance. If they match, the address value output from the address generation circuit 39 is output to the selection circuit 4
0 is selected and output to the buffer memory 19.

The method of generating the address output from the address generation circuit 39 will be described with reference to the flowchart of FIG.

The address generation circuit 39 is a bus arbitration unit 17
Depending on the service type output from the device, the master device for which access is permitted is determined by the communication control unit 18, the DMAC 15, or the MPC.
It is determined which of U14 is the case (step 51).

If the service type is the communication control means 18, the value of the communication control means access address 35 is output (step 52). After the access is completed, the value of the communication control means access address 35 is equal to the reception area final address 34. It is determined whether or not they match (step 53). If they do not match, the value of the communication control means access address 35 is incremented (step 54). Is set (step 55).

When the service type is DMAC15, D
The value of the MAC access address 36 is output (step 5).
6) After the access is completed, the DMAC access address 36
Is determined to be equal to the reception area final address 34 (step 57). If they do not match, the value of the DMAC access address 36 is incremented (step 58).
Is set to the value of the reception area start address 33 (step 59).

On the other hand, when the service type is MPU, M
The value of the PU access address 36 is output (step 6).
0), the data length read by the MPU 14 is fetched into the reception data length 38 in the address conversion means 20, and whether or not the next reception data has been returned to the head of the reception area is determined from this data length. 34 and MP
A determination is made by comparing the value of the U access address 36 with the sum of the received data length 38 (step 61).

In this determination, the value of the reception area final address 34 is the value of the MPU access address 36 and the reception data length 3
If the value is equal to or less than the sum of the MPU 8 and the MPU 14, the MPU 14 accesses the buffer memory 19 once since it reaches the end of the reception area and continues to access from the beginning of the reception area. As the value of the MPU access address 36 at the time of access, a value calculated by (reception area start address 33+ (reception data length 38- (reception area end address 34-MPU access address 36))) is set (step 62).

On the other hand, if the value of the receiving area final address 34 is larger, M is set as the leading address value of the next data.
The sum of the value of the PU access address 36 and the received data length 38 is set as the MPU access address 36 (step 63).

[0029]

As described above, according to the present invention, when receiving data is transferred in the data communication device, the address conversion means can access the predetermined receiving port from the master device so that the address translating means can buffer the data. Since the address of the receiving area on the memory is determined, it is not necessary for each master device accessing the buffer memory to individually calculate the buffer memory address, and it is not necessary to perform the address calculation processing by the MPU and the setting of the transfer source address for the DMAC Therefore, an increase in the DMA processing load and a decrease in the DMA transfer performance can be prevented, and the data transmission processing performance can be improved.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a data communication device in an embodiment according to the present invention.

FIG. 2 is a block diagram of a transmission system in an embodiment according to the present invention.

FIG. 3 is a diagram illustrating an operation of an address conversion unit when an MPU accesses a reception area of a buffer memory.

FIG. 4 is a diagram illustrating an operation of an address conversion unit when a DMAC or a communication control unit accesses a reception area of a buffer memory.

FIG. 5 is a schematic diagram showing the operation of the address conversion means when the MPU accesses beyond the last address of the reception area of the buffer memory.

FIG. 6 is a diagram showing the operation of the address conversion means when the DMAC accesses beyond the last address of the reception area of the buffer memory.

FIG. 7 is an operation flowchart when an access request is accepted in the address generation circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Transmission line, 2-4 ... Computer, 5-7 ... Data communication device, 11 ... CPU, 12 ... Host memory, 13 ... System bus, 14 ... MPU, 15 ... DMAC, 17 ... Bus arbitration means, 18 ... Communication Control means 19 buffer memory
20 ... Address conversion means.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kenichi Yoneda 5-2-1 Omikacho, Hitachi City, Ibaraki Prefecture Inside the Omika Plant, Hitachi, Ltd. (72) Inventor Hiroshi Tomizawa 5-chome, Omikamachi, Hitachi City, Ibaraki Prefecture No. 1 Hitachi, Ltd., Omika Plant (72) Inventor Ryo Nitta 5-2-1, Omika-cho, Hitachi City, Ibaraki Pref.

Claims (4)

[Claims] 1. A transmission system for transmitting data between a plurality of data communication devices connected to a transmission line, comprising an MPU,
A data communication device comprising a DMAC, a communication control means, a buffer memory for storing transmission / reception data, a bus arbitration means for granting access permission in response to an access request output from the MPU and the DMAC, wherein the MPU and the DMAC are buffer memories. When accessing the device, the bus arbitration unit outputs a device type to which access is granted, and accesses the buffer memory according to the device type output from the bus arbitration unit. Address conversion means for generating an address when the communication is performed, the address conversion means comprising: the communication control means;
A data communication device, which performs address conversion when there is an access request to the predetermined address from U or the DMAC. 2. The data communication apparatus according to claim 1, wherein said address conversion means stores a start address and a last address of a reception area of said buffer memory for storing data received from a transmission line, Each time an access is made from the means and the DMAC, an address for accessing the buffer memory is sequentially incremented, and if the address for accessing the buffer memory matches the last address, a next read access request from the DMAC is made. A data communication device for converting an address to be generated into the head address. 3. The data communication device according to claim 1, wherein said address translating means comprises said communication control means or said M.
At the time of an access request from the PU, an address storing the data length of the received data is generated, the data value read by the MPU is taken into the address conversion means, and the data length of the next received data is stored. A data communication device for calculating an address. 4. The data communication device according to claim 1, wherein a data length of the received data is stored at a head of the received data stored in the buffer memory, and the data length read in advance is stored in the DMAC. After the setting, the DMA is accessed so as to access from a predetermined address.
A data communication device, wherein the data communication device activates C.