JP2001256169A - Data transfer control system and device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To effectively utilize plural look-ahead mechanism in a system provided with the look-ahead mechanism for locking data ahead from a memory and preparing for a read request from a master. SOLUTION: At the time of requesting data transfer to an input/output device 20, a device driver selects the look-ahead mechanism 306 to be used for the transfer, sets it to the device 20 and sets a look-ahead method to be used by the look-ahead mechanism 306 to a look-ahead method specifying register part 308. At the time of performing read access through a system bus 10, the input/ output device 20 outputs a signal for indicating the look-ahead mechanism 306 set to the device driver together with a requesting address. A look-ahead mechanism identification mechanism 304 generates a selection signal to the look-ahead mechanism 306 corresponding to the signal. Thus, the selected look- ahead mechanism 306 responds to the request. An appropriate look-ahead method is set to a free look-ahead mechanism 306 and it is utilized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for transferring data between a memory and various devices such as an input / output device, and more particularly, to a technique for prefetching data from a memory efficiently during a DMA transfer. About technology.

[0002]

2. Description of the Related Art There has been known a system in which a memory controller is provided with a prefetch (prefetch) mechanism in order to improve transfer performance when reading a memory from an input / output device. An example of such a system is disclosed in, for example, Japanese Patent Application Laid-Open No. 6-324986. In this conventional system, a data transfer device is provided between a system bus and a memory. When there is a read access for a certain address from the input / output device on the system bus to the memory, the data transfer device reads data larger than the required size of the input / output device from the memory. The data transfer device transfers only the requested size of the read data to the input / output device, and stores the remaining portion in the prefetch buffer. The process of storing data in the prefetch buffer is performed in the background. Then, when there is a continuous read access to the next address from the input / output device, the data transfer device transfers the data at that address stored in the prefetch buffer to the input / output device.

Generally, it is faster to read data from a prefetch buffer than to read data from a memory. Therefore, according to the above-described conventional system, an apparently high-speed read access can be performed from an input / output device.

However, the above-mentioned conventional system has only one prefetch buffer mechanism,
In the case of random access or the case where access is made from a plurality of input / output devices at the same time, there is a problem that the effect cannot be obtained.

On the other hand, Japanese Unexamined Patent Publication No. Hei 8-272732 discloses a system in which a plurality of prefetch buffer mechanisms are provided so as to be able to cope with random access and accesses from a plurality of input / output devices to some extent. There is something. In this system, when there is a second access to a continuous address, it is determined that prefetch should be performed, and an empty prefetch buffer mechanism is selected to perform prefetch processing.

[0006]

Problems to be Solved by the Invention
The technique of Japanese Patent Publication No. 2 has the following problems.

First, in this prior art, it is necessary to provide a one-to-one prefetch buffer mechanism for the connected input / output devices, and since the association is fixed, the expandability and the processing flexibility are reduced. There's a problem. For example, one prefetch buffer mechanism cannot be efficiently allocated to a plurality of input / output devices.

In the above-mentioned prior art, whether or not to perform prefetching is determined based on the continuity of the previous request address and the current request address. Therefore, at the time of the first request of a series of data transfer requests, There is a problem that the prefetch mechanism does not work.

The present invention has been made to solve such a problem, and an object of the present invention is to provide a data transfer control system and apparatus capable of providing a prefetch process flexibly to a plurality of devices. I do. Also,
An object of the present invention is to provide a mechanism that can quickly start prefetching processing.

[0010]

SUMMARY OF THE INVENTION A data transfer control system according to the present invention is a transfer control system for transferring data between a memory and a plurality of devices. A plurality of pre-reading means for responding to the data of the address requested to be read from the device if the data is in the buffer, and device control means for controlling the device, wherein the device Device control means for selecting a read-ahead means to be used for the read processing from the plurality of read-ahead means when performing the read processing, and, when a read request is received from the device, the device control means for the device. Identifies the prefetching means selected by the user and causes the prefetching means to respond to the read request. And means, the.

According to this configuration, the prefetch means can be dynamically allocated to a plurality of devices such as input / output devices and used, and the equipped prefetch means can be used effectively. Also, the selected prefetch means can start prefetch processing immediately upon the first read request from the device, so that a prefetch effect can be obtained earlier than in the prior art.

In a preferred aspect, each of the prefetching means is capable of coping with a plurality of prefetching methods, and has a function of prefetching data from the memory by using a prefetching method set from outside. The device control means selects the prefetch means to be used and, at the same time, selects and sets a prefetch method corresponding to the read processing for the selected prefetch means.

According to this aspect, the same prefetching means can be used by a plurality of prefetching methods according to the contents of data transfer, so that the prefetching means can be effectively used.

In another preferred aspect, the device control means sets identification information indicating the selected read-ahead means to a corresponding device, and the device sets the identification information from the device control means upon a read request. The identification information of the read-ahead means is output, and the identification means identifies the read-ahead means responding to the request based on the identification information output by the device at the time of the read request.

In this aspect, if the higher-order bits of the address not used in the address space of the memory are used as the identification information indicating the selected look-ahead, the request address can include the designation of the look-ahead. , The cycle of the read request can be shortened.

In another preferred aspect, the identification means stores a correspondence relationship between the prefetch means selected by the device control means and the device corresponding thereto, and the prefetch means corresponding to the device which has issued the read request. Are identified from the correspondence.

According to this aspect, the device control means includes:
What is necessary is just to set the selected prefetch means as the identification means, and it is not necessary to set the device via a bus or the like.

In a further preferred aspect, the device control means sets a start address of the read processing for the selected prefetch means in addition to the prefetch method, and the selected prefetch means sets the start address of the device. Upon receiving the setting of the prefetching method and the start address from the control means, the prefetching process is started without waiting for a read request from the device.

According to this aspect, prefetching can be started before the first read request from the device arrives, so that the time-consuming memory read process is almost completely hidden from the viewpoint of the device, and high-speed prefetching means The processing speed is improved because only reading from the memory is sufficient.

Further, the system according to the present invention is a transfer control system for transferring data between a memory and a device, which can support a plurality of prefetching methods, and uses a prefetching method designated therein. A plurality of pre-reading means for pre-reading data from the memory and accumulating the data in a buffer, and responding to the data of the address requested by the device if the data is in the buffer, and a device control means for controlling the device. And a device control means for selecting and setting a prefetch method corresponding to the read processing to the prefetch means when causing the device to perform a read process from the memory.

According to this configuration, the same prefetching means can be used by a plurality of prefetching methods according to the contents of data transfer, so that the prefetching means can be effectively used.

An apparatus according to the present invention is an apparatus for controlling data transfer between a memory and a plurality of devices,
A plurality of read-ahead means for pre-reading data from the memory and accumulating the data in a buffer, and responding to the data at the address requested by the device if the data is in the buffer; and a device control means for controlling the device. A means for receiving a selection of the prefetch means used by the device for read processing, and, when a read request is received from the device, identifying the prefetch means selected by the device control means for the device; For responding to the read request.

With this apparatus, the prefetch means can be dynamically allocated to a plurality of devices for use, and the prefetch means can be effectively utilized.

[0024]

Embodiments of the present invention (hereinafter referred to as embodiments) will be described below with reference to the drawings.

FIG. 1 is a block diagram schematically showing a hardware configuration of a data transfer system according to the present invention.
This figure shows the memory device 4 in the computer system.
FIG. 2 shows a portion related to data transfer between the input / output device 20 and the input / output device 20.

In FIG. 1, a system bus 10 is a bus for connecting various control mechanisms (such as a CPU) and an input / output device 20 (such as an HDD and a network card) constituting a computer system.
It has signal lines for data and control signals. The control mechanism and the input / output device 20 communicate with the system bus 10 through communication according to a predetermined protocol.
Exchange data with each other via

Here, for convenience of explanation, a system having a general bus structure will be described as an example, but the system of the present invention employs a connection system other than the bus connection system, for example, one-to-one hub connection. It is also applicable to systems.

The system bus 10 is, for example, a data bus (CP) having a number of bits approximately equal to the data width of a CPU (not shown).
U data width may be equal to, greater than, or smaller than U data width), and an address bus having the number of bits necessary to represent the address space of the CPU, and arbitration (bus arbitration) and DMA cycles , C
Generate PU cycle, DMA cycle or CPU
It has control lines used to respond to cycles and signal interrupts. Here, the CPU cycle is C
A PU is a cycle in which a PU reads and writes to a peripheral input / output device and a memory device. A DMA cycle is a cycle in which a device other than the CPU reads or writes to a memory device.

Each input / output device 20 has a bus master DMA function of performing a DMA transfer with the memory device 40 by itself becoming a bus master. When the input / output device 20 becomes a bus master and starts a bus cycle operation, the input / output device 20 sends an address to which an access request is made, a chip select signal for the memory device 40, and a control signal indicating a cycle start to the system bus 10. The input / output device 20 takes in data from the bus 10 in a read cycle, and supplies data to the bus 10 in a write cycle.

The data transfer device 30 is provided between the memory device 40 and the system bus 10, and controls data transfer (write, read) from the input / output device 20 to the memory device 40. This data transfer device 30
Are the slave control mechanism 302 and the prefetch mechanism identification mechanism 30
4. A plurality of prefetching mechanisms 306, a prefetching method designation register section 308, an arbitration mechanism 310, and a memory controller 31
2 is provided.

The slave control mechanism 302 recognizes the chip select signal from the bus master (input / output device 20), and if it indicates an access to itself, performs a process for responding to the access. here,
If the access is a read access to the memory device 40 and one of the prefetch mechanisms 306 is selected by the prefetch mechanism identification mechanism 304 described later, the slave control mechanism 302 reads the selected prefetch mechanism 306. Request a cycle. Then, the data responded from the prefetch mechanism 306 is transferred to the input / output device 20 which is a bus master.

On the other hand, if the access from the input / output device 20 is a write access, or if the prefetch mechanism identification mechanism 304 does not select the prefetch mechanism 306 even if the access is a read access, the slave control mechanism 302 Arbitration mechanism 3 for write or read cycle to 40
Request for 10. This case is a process unrelated to the prefetching process, and the prefetching mechanism 306 is not used. The slave control mechanism 302 performs read or write processing on the memory device 40 via the arbitration mechanism 310 and the memory controller 312 in response to a request from the input / output device 20.

In response to an access request from the input / output device 20, the prefetch mechanism identification mechanism 304 selects a prefetch mechanism corresponding to the input / output device 20 from a plurality of prefetch mechanisms 306, and responds to the prefetch mechanism 306. The selected signal is output. The slave control mechanism 302 identifies the selected pre-reading mechanism 306 by the selection signal. For this selection, a mechanism for identifying a prefetch mechanism 306 corresponding to the input / output device 20 from an access request of the input / output device 20 is implemented in the prefetch mechanism identification mechanism 304.

In a preferred embodiment, the upper bits of the request address of the input / output device 20 are used to specify the prefetch mechanism 306. For example, in the present system, a 32-bit address is used, and the actual address space of the memory device 40 is 0x0h.
It is assumed that the size is 16 Mbytes of ~ 0xFFFFFFh. In this case, 24 bits are sufficient to specify the address of the memory device 40. In the present embodiment, the lower 24 bits of the 32-bit address are used as the address of the memory, and the remaining upper 8 bits are used to specify each prefetch mechanism 306. Used for In this case, the pre-reading mechanism identifying mechanism 304 has
Implements the correspondence between the upper address value and the look-ahead mechanism as shown in the table. In the table illustrated in FIG. 2, for example, the upper 8 bits of the address of 0x80h are associated with the 0th look-ahead mechanism. The upper 8 bits 0x0h of the address are allocated for access without using the prefetch mechanism.

More specifically, for example, the prefetching mechanism identification mechanism 304 includes a register in which the upper 8 bits of the corresponding address are set for each of the prefetching mechanism 306 and the case of “no prefetching”. Each of the registers includes a comparator for comparing the upper 8 bits of the request address received from the bus master with the value of the register. The output signal line of each of these comparators is
02 is input. The slave control mechanism 302 determines which of the comparators is turned on and determines which of the prefetch mechanism 3
06 (or a request not using the prefetching mechanism).

In the data transfer device 30, a table as shown in FIG. In this table, a use flag indicating whether or not the prefetch mechanism is used is provided for each prefetch mechanism. If the flag is 0, it is currently unused,
If it is 1, it is in use.

In the present embodiment, when starting a data transfer process between the memory device 40 and one of the input / output devices 20 in accordance with an instruction from an operating system or the like, the device driver of the input / output device 20 is configured as shown in FIG. 3, one unused one (that is, one whose flag is 0) is selected from the pre-reading mechanism 306 and assigned to the input / output device 20. That is, the device driver notifies the input / output device 20 of the value of the upper 8 bits of the address corresponding to the selected prefetch mechanism 306. The above is the processing when prefetching is performed, and when prefetching is not performed (in the case of writing to the memory device 40, or in the case of transfer processing that does not require prefetching even in the case of reading from the memory device 40).
Notifies the input / output device 20 that performs the transfer processing of the upper 8 bits of the address (0x0h in FIG. 2) when the prefetch mechanism is not used. The input / output device 20, which has received the upper address value, adds the 8-bit value to the upper address of the memory address (24 bits) to be accessed when requesting each bus cycle until the transfer processing is completed. It is sent out as a bit request address. In response to this, the data transfer device 30 sets the pre-reading mechanism identifying mechanism 30
4 examines the upper 8 bits of the request address, refers to the identification table, and selects the corresponding prefetch mechanism 306 (or determines that the prefetch mechanism is not used).

Each prefetch mechanism 306 has a prefetch buffer (not shown). Each of the prefetch mechanisms 306 has a built-in function corresponding to a plurality of prefetch methods, and performs a prefetch (prefetch) process using a designated method among the plurality of prefetch methods. Examples of the prefetching method include “increment sequential” in which an address is sequentially incremented by a constant value and prefetching is performed, and “decrement sequential” in which an address is decremented by a constant value and prefetched is performed. Also,
For example, there is a case where the increment of the address increment is different even for the same increment sequential. If a code is allocated to each of these cases in advance, the prefetching method can be designated by the code.

If the data at the address requested by the master (in this example, the slave control mechanism 302) is not in the prefetch buffer, the prefetch mechanism 306 becomes the master and requests the arbitration mechanism 310 for a read cycle. The memory device 40 via the memory controller 312
, The data of the requested address is read out, and a slave response is made to the slave control mechanism 302 using the data. Then, even after reading the data at the requested address from the memory device 40, the prefetching mechanism 306 continues
A prefetch address is obtained according to a prefetch method specified in advance, and the data at this address is similarly read from the memory device 40 and stored in its own prefetch buffer. This prefetching / accumulating process is repeated as long as the prefetch buffer does not become full.

On the other hand, if the data of the address of the read request accepted from the master (in this example, the slave control mechanism 302) is already stored in its own prefetch buffer, the prefetching mechanism 306 uses the data to make the master Immediately responds to the request. When the master requests the next address after the previous request address after the above-mentioned prefetching process is started, the data at that address is already stored in the prefetch buffer, so that the data is output.

In FIG. 1, the data transfer device 30 is provided with four prefetch mechanisms 306, but this is merely an example, and the prefetch mechanism 306 incorporated in the transfer device 30 is only an example.
The number is not limited to this.

The prefetching method designation register section 308 includes a register for designating a prefetching method for each of the prefetching mechanisms 306 provided in the transfer device 30. These registers are registers that can be set from the CPU. In the present embodiment, when the device driver issues an instruction for data transfer processing to the input / output device 20, the prefetch mechanism 30 to be used is used.
When 6 is selected (described above), the code of the prefetching method to be used is set in the register corresponding to the prefetching mechanism 306 in the prefetching mechanism designation register unit 308. Thus, when a request for a DMA transfer cycle comes from the input / output device 20 thereafter, the selected look-ahead mechanism 306 is selected.
Can execute a prefetch process according to a prefetch method specified in a corresponding register. The register unit 308
Since a register is provided for each prefetch mechanism 306, a prefetch method can be individually set for each prefetch mechanism 306.

The arbitration mechanism 310 includes a plurality of prefetch mechanisms 30.
6 and a mechanism for arbitrating access from the slave control mechanism 302 to the memory controller 312. Arbitration mechanism 3
10 sequentially receives cycle requests from the selected master (in this case, one of the plurality of read-ahead mechanisms 306 and the slave control mechanism 302), and based on the received cycle request information, The controller 312 requests a read or write cycle as a master.

The memory controller 312 includes the arbitration mechanism 3
The information of the various cycle requests received from 10 is converted into the address of the real memory of the memory device 40, and the access to the real memory is controlled. Further, if control specific to the memory device 40 such as refreshing is required, the control is executed.

The system configuration of the present embodiment has been described above. Next, the flow of data transfer processing by this system will be described.

First, when it becomes necessary to transfer data between any of the input / output devices 20 and the memory device 40 in accordance with the processing of the application or the OS, a device driver corresponding to the input / output device 20 is used. It starts up and performs necessary control processing for transfer processing on the input / output device 20 and the like. FIG. 4 shows the flow of the processing. In this case, the device driver first determines whether to perform prefetching in the transfer processing (S10). In the case of writing from the input / output device 20 to the memory device 40, or in the case of reading from the memory device 40, if the content of the transfer process has a small prefetch effect, the result of this determination is No.
On the other hand, in the case of reading from the memory device 40, if the pre-reading is effective such as the transfer of data having a large continuous address size, the determination result in S10 is Yes. The device driver makes the determination in S10 according to the content of the read or write request from the OS or the like.

If it is determined in S10 that prefetching is to be performed,
The device driver refers to the use status table (see FIG. 3) provided in the transfer device 30 and selects one to be used from the available prefetching mechanisms 306 (S12).
The code of the prefetching method to be applied is set in the register of the prefetching method designation register unit 308 in the selected prefetching mechanism 306 (S14). Since the device driver knows which prefetching method to apply from the content of the request from the OS or the like, the method may be set. Then, the device driver instructs the input / output device 20 to perform a data transfer process (S16). At this time, in addition to the contents of the transfer processing such as the transfer direction, the start address, and the total transfer size, the value of the address high-order bit corresponding to the prefetch mechanism 306 selected in S12 is notified to the input / output device 20.

On the other hand, if it is determined in S10 that the prefetching process is not to be performed, the device driver issues a transfer instruction including an address upper bit value (0x0h in the example of FIG. 2) indicating that the prefetching mechanism is not used. Is performed on the input / output device 20 (S16).

The input / output device 20, which has received the transfer instruction in S16, becomes a bus master and requests the system bus 10 repeatedly for a DMA transfer cycle until the transfer of the data of the specified size is completed. At this time, the input / output device 20 makes the request by setting the notified upper bit value of the address to the upper address of the bus request.

Next, the flow of DMA read processing from the input / output device 20 to the memory device 40 will be described using a specific example. In this example, a case will be described in which two input / output devices 20 (hereinafter, referred to as a bus master A and a bus master B) perform a DMA read to the memory device 40 at the same time.

In this example, the bus master A has the address 0
1 in ascending order from x100000h to 0x1FFFFFh
It is assumed that the corresponding device driver has instructed the DMA read of the M-byte memory block. The bus master B has the address 0x2FFFFF
Assume that the corresponding device driver instructs to DMA-read a 1 Mbyte memory block in descending order from h to 0x200000h. At this time, the prefetch mechanism 3 used by the bus masters A and B has already been used.
06 is selected by each device driver, and the value of the address high-order bit indicating the prefetch mechanism 306 has been notified to the bus masters A and B, respectively. In this example, it is assumed that the prefetch mechanism 0 (upper address 0x80h) is selected for the bus master A, and the prefetch mechanism 1 (upper address 0xF0h) is selected for the bus master B. Further, the prefetching method designation register unit 308
It is assumed that an appropriate prefetching method is set by the device driver for each of the selected prefetching mechanisms 306. That is, in this example, a code indicating the increment sequential read ahead is set in the register of the prefetch mechanism 0 used by the bus master A, and a code indicating the decrement sequential is set in the register of the prefetch mechanism 1 used by the bus master B. ing. Then, it is assumed that the bus masters A and B request the right to use the bus on the system bus 10 almost simultaneously, and the bus master A first obtains the right to use as a result of the arbitration.

Then, the bus master A starts a memory read cycle (DMA transfer cycle) by specifying the address 0x80100000h on the acquired bus. Of these addresses, the upper 8 bits 0x80 indicate the prefetch mechanism 0, and the lower 24 bits indicate the address of the real memory. This real memory address 0x100
000h is the first address of the requested 1 Mbyte transfer. When the memory read cycle is started, the slave control mechanism 302 of the data transfer device 30 recognizes that it is selected by the chip select signal. In parallel with this, the prefetch mechanism identification mechanism 304 compares the upper 8 bits of the request address with the address values of the registers corresponding to each of the prefetch mechanisms 0 to 3 and “no prefetch”. As a result, the prefetch mechanism identification mechanism 304 issues a selection signal for selecting the prefetch mechanism 0 to the slave control mechanism 302. Upon receiving this, the slave control mechanism 302 sends the address 0x1000 to the prefetch mechanism 0 as a master.
A read request of 00h is made.

In the prefetch mechanism 0 receiving this request, the requested address is the first address of a series of transfer data, and the corresponding data does not exist in the prefetch buffer. For this reason, the prefetch mechanism 0 misses the request address, and as a result, becomes a master and propagates the read request to the arbitration mechanism 310.

When the read cycle is permitted by the arbitration mechanism 310 and the data requested by the slave control mechanism 302 has been read from the memory device 40, the prefetch mechanism 0
Writes that data to its prefetch buffer. Then, even after the writing is completed, according to the prefetching method set in the prefetching method designation register unit 304,
The data of the subsequent address is prefetched from the memory device 40, and the prefetched data is stored in the prefetch buffer. This prefetching process is continued until the prefetch buffer becomes full.

The data read from the memory device 40 by the pre-reading mechanism 0 is transmitted to the slave control mechanism 3 which is the request source.
02. This supply is performed in parallel with the above-described prefetching process. The slave control mechanism 302
The supplied data is supplied to the bus master A which is the data request source.

Next, when the bus master B acquires the right to use the system bus 10, the bus master B becomes 0xF02FF.
A memory read request is issued from the FFF. As a result, the same processing as in the first DMA transfer cycle from the bus master A described above is performed. In this case, the upper 8 bits of the request address indicate the prefetch mechanism 1, and the lower 24 bits indicate the first address of the transfer data requested by the device driver. Therefore, the prefetch mechanism 1 is activated and the prefetch process from the memory device 40 is started, and the data read first is supplied to the requesting bus master B via the slave control mechanism 302.

After the bus masters A and B have received the first transfer data in this manner, when the next bus master A or B makes a read request for the next address, the corresponding prefetch mechanism 0 or 1 sends the next address to the corresponding prefetch mechanism 0 or 1. Data is stored. Therefore, in this case, the prefetch mechanism 0 or 1 that has received the read request from the slave control mechanism 302
The requested data is retrieved from its own prefetch buffer and supplied to the slave control mechanism 302. And
This data is supplied from the slave control mechanism 302 to the requesting bus master.

Therefore, in the present embodiment, in the first cycle of a series of memory reads from the bus master, data is read directly from the memory device 40.
In the subsequent cycles, the data stored in the prefetch buffer is read. That is, in the second and subsequent cycles, the operation of the read-ahead mechanism reading data from the memory device 40 and the operation of the read-ahead mechanism responding to the bus master via the slave control mechanism 302 are separated. , The speed of the memory read is increased from the viewpoint of the bus master.

As described above, according to this embodiment, a plurality of prefetch mechanisms 306 are provided in the data transfer device 30 and these prefetch mechanisms 306 are dynamically assigned to requests from the input / output device 20. So you can
For example, even when the number of prefetch mechanisms is smaller than the number of input / output devices 20, the prefetch mechanisms can be efficiently allocated to the input / output devices 20 and used.

In the present embodiment, each prefetch mechanism 30
In No. 6, the prefetching method is not fixed, and a method dynamically selected from several pre-installed methods can be executed. Therefore, the prefetching mechanism can be used efficiently. That is, for example, even if the prefetch mechanism is empty, there is no possibility that the prefetch method cannot be used because the prefetch method does not match.

In this embodiment, each prefetch mechanism 30
6 can perform a prefetch operation independently of other prefetch mechanisms.

In this embodiment, each prefetch mechanism 30
In the case of No. 6, since the prefetching method has already been set by the device driver when a series of memory reads starts, the prefetching process can be started from the first read access. In the technique disclosed in Japanese Patent Application Laid-Open No. 8-272732, it is determined whether or not to perform prefetching at the time of the second access to a continuous address. Therefore, the effect of prefetching is obtained only after the third access. On the other hand, in the present embodiment, prefetching is performed from the first access, so that a prefetch effect can be expected from the second access.

The preferred embodiment of the present invention has been described above. The embodiment described above is merely an example of the embodiment of the present invention, and various modifications can be considered within the scope of the present invention.

[Modification 1] For example, the following is conceivable as another example of the identification method of the prefetch mechanism identification mechanism 304. In this method, unused upper bits of the address are fixedly assigned to each input / output device 20.
Then, the data transfer device 30 is provided with a table as shown in FIG. In this table, for each of the prefetch mechanisms 0 to 3, an input / output device 20 (that is, an upper address bit corresponding to the input / output device) using the prefetch mechanism is set. A value indicating unused (for example, a null value) is set for a prefetch mechanism that is not used. The device driver is
The use / non-use of the prefetch mechanism can be known from the table of FIG. 5, and an unused prefetch mechanism can be selected. When the device driver selects the look-ahead mechanism 306 used by the input / output device 20, the device driver
In this table, the upper address corresponding to the input / output device 20 is set in the column of the selected look-ahead mechanism.

When issuing a request to the bus 10, the input / output device 20 sets a value fixedly assigned to itself to an upper address. Prefetching mechanism identifying mechanism 304 receiving this
Checks whether or not an entry matching the upper 8 bits of the request address is entered in the table (FIG. 5), and if so, outputs a corresponding prefetch mechanism selection signal.

In the case of data transfer without prefetching,
The device driver does not set the address of the input / output device in the table of FIG. Therefore, in this case, when a request comes from the input / output device, the look-ahead mechanism selecting mechanism 304 outputs a selection signal indicating that the look-ahead mechanism is not used, because there is no address value corresponding to the device in the table.

[Modification 2] Further, the prefetching mechanism identifying mechanism 3
As the selection method 04, a method using a bus use grant signal (bus grant) is also possible. FIG. 6 shows an example of a system configuration using this method. 6, the same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

The bus cycle request of each input / output device 20 is arbitrated by the bus arbiter 50. Here, a bus use grant signal (bus grant) line extending from the bus arbiter 50 to each of the input / output devices 20 is branched and input to the prefetch mechanism identification mechanism 304. This allows
The prefetch mechanism identification mechanism 304 can identify the accessing input / output device 20 depending on which of the bus use permission signal lines from the arbiter 50 is turned on.

In this modification, the data transfer device 3
0 has the same table as in the first modification described above,
When the device driver selects the prefetch mechanism used for data transfer, the device driver sets the number of the corresponding input / output device in the column of the prefetch mechanism in the table. Therefore, when the input / output device can be identified by the bus permission signal, the prefetch mechanism identification mechanism 304 can identify the corresponding prefetch mechanism (or can determine that the prefetch is not performed).

In Modification 2 and Modification 1 described above, 1
A plurality of prefetch mechanisms can be simultaneously associated with one input / output device 20. In this case, the device driver of the input / output device may select a plurality of prefetch mechanisms and set the number of the device in the column of the prefetch mechanism in the table. Know what you have). This mechanism is effective in the following cases.

That is, in the input / output device 20,
There is a circuit configuration having a plurality of bus masters inside. When an address in a completely different section is independently requested from each bus master in the device 20 as described above, the data transfer device 30 receives a request from the data transfer device 30 even though each internal bus master requests a continuous address. It may appear that only one input / output device 20 requests a different address. In such a case, prefetching can be realized by selecting the prefetch mechanism 306 for the input / output device 20 by the number of internal bus masters.

When there is a read request from the input / output device 20, the prefetch mechanism identification mechanism 304 supplies a selection signal indicating the selected plurality of prefetch mechanisms 306 to the slave control mechanism 302. Slave control mechanism 3
No. 02 requests read cycles to the plurality of prefetch mechanisms 306 in a predetermined order. If data in the prefetch buffer is hit by any of the prefetch mechanisms 306, the process does not proceed to the subsequent prefetch mechanism 306. In this way, while hitting the plurality of prefetch mechanisms 306 in a predetermined order, the first mistake occurs in the prefetch mechanism 306.
Will be in charge of prefetching from that address.

[Modification 3] For example, the memory device 40
If the address space of the real memory is the same as the address size of the bus 10, the above-described method of using an unused upper address for selecting a prefetch mechanism cannot be used as it is.

In such a case, the address space may be divided into a plurality of parts, and the prefetch mechanism 306 may be assigned to each divided space. In this case, the prefetch mechanism identification mechanism 304 can automatically select the prefetch mechanism 306 that is in charge of the address section from the upper bits of the request address of the input / output device 20.

By assigning a plurality of prefetch mechanisms to each divided section, it is possible to cope with a case where the same divided section is accessed from a different bus master.
Greater flexibility.

[Modification 4] In the above embodiment, prefetching is started only after the first read access from the input / output device 20, but prefetching is started without waiting for the first read access. Is also possible.

That is, in this modification, when the device driver selects the prefetching mechanism 306 and sets the prefetching method in the register unit 308, the prefetching mechanism 306 starts the prefetching process. In this case, the prefetch mechanism 306
Starts prefetching without waiting for the first request address from the input / output device 20. Therefore, when the device driver selects the prefetching mechanism 306, the device driver itself performs prefetching on the prefetching mechanism 306. Set the start address of the process.

According to this modification, the input / output device 20
The requested data exists in the prefetch mechanism 306 from the time of the first read access from the
0 means that data is read from the prefetch mechanism 306 from the beginning to the end. Therefore, the process of reading data from the real memory is completely hidden from the input / output device 20, and a high-speed read process can be realized.

[Fifth Modification] In the above-described embodiment, two types of prefetching methods supported by the prefetching mechanism 306 have been described: increment sequential and decremental sequential. However, other prefetching methods can be employed. As another look-ahead method, for example, there is a cache method, a ring buffer method, or the like.

The cache system is a system in which every time data at the address requested by the master is missed (not in the prefetch buffer), a block of a predetermined size starting from the address is prefetched and stored in the prefetch buffer. If the prefetch buffer is full, L
Old data is replaced with new data by a known method such as the RU method. As a result, frequently used data having high locality can be stored for a long time. This method can provide a certain level of read-ahead effect even when the address requested by the bus master cannot be predicted.

In the ring buffer system, a data start address and a return address are set, and when prefetching is completed up to the return address, the control returns to the start address, and the same block (from the start address to the return address) is cyclically repeated. This is a prefetching method.

As described above, by incorporating various prefetching methods into the prefetch mechanism 306 and making them available selectively, prefetching can be executed for various types of data transfer.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a schematic configuration of a data transfer system according to an embodiment.

FIG. 2 is a diagram showing a correspondence between a prefetch mechanism and upper bits of an address.

FIG. 3 is an example of a table showing a use state of a prefetch mechanism.

FIG. 4 is a flowchart illustrating a processing procedure of a device driver.

FIG. 5 is an example of a table used in another look-ahead mechanism identification method.

FIG. 6 is a diagram illustrating a system configuration of a modification in which a prefetch mechanism is identified by a bus use permission signal.

[Description of Signs] 10 system bus, 20 input / output devices, 30 data transfer devices, 40 memory devices, 302 slave control mechanism, 304 prefetch mechanism identification mechanism, 306 prefetch mechanism, 308 prefetch method designation register section, 310 arbitration mechanism, 312 Memory controller.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Ichikawa Kawasome 3-1-1 Honcho, Iwatsuki-shi, Saitama WAT SU Building West Building 4F Fuji Xerox Co., Ltd. In-house (72) Inventor Yuji Yoshino 3-chome, Honcho, Iwatsuki-shi, Saitama No. 1-1 WAT SU Building West Building 4F Fuji Xerox Co., Ltd. In-house (72) Inventor Kei Hatano 3-1-1 Honcho, Iwatsuki-shi, Saitama Prefecture WAT SU Building West Building 4F Fuji Xerox Co., Ltd. In-house (72) Inventor Harunobu Miyashita Saitama 3-1-1, Honcho, Iwatsuki-shi, WAT SU Building West Building 4F, Fuji Xerox Co., Ltd. In-house (72) Inventor Takahiro Iwabuchi 3-1-1, Honmachi, Iwatsuki-shi, Saitama 4F WAT SU Building West Building 4F, Fuji Xerox Co., Ltd. In-house F-term (Reference) 5B014 EA03 EB01 FA16 GC04 GC07 GC23 GD05 GD14 GD22 GD23 GD34 5B060 CA06 CB01 5B061 BA01 BA03 BB03 DD01 DD09 DD11 PP01 5B077 AA14 AA18 BA02 BB03 BB05 DD05 DD11 DD22

Claims (11)

[Claims] 1. A transfer control system for transferring data between a memory and a plurality of devices, wherein data is pre-read from the memory and stored in a buffer, and data at an address requested to be read from the device is provided. A plurality of prefetch means for responding to the data if the data is in the buffer; and a device control means for controlling the device, wherein the plurality of prefetch means are provided when the device performs a read process from the memory. A device control unit for selecting a prefetch unit to be used for the read processing from the device, and when receiving a read request from the device, identifies the prefetch unit selected by the device control unit for the device. A data transfer control system comprising: identification means for responding to the read request; 2. The device control means, wherein each of the prefetch means is capable of coping with a plurality of prefetch methods, and has a function of prefetching data from the memory by a prefetch method set from outside. 2. The data transfer control system according to claim 1, wherein, at the same time as selecting the prefetching means to be used, a prefetching method corresponding to the read processing is selected and set for the selected prefetching means. 3. The device control means sets identification information indicating the selected prefetch means in a corresponding device, and the device identifies the prefetch means set by the device control means at the time of a read request. 2. The data transfer control according to claim 1, wherein the information is output, and the identification unit identifies, based on the identification information output at the time of the read request, the read-ahead unit that responds to the request. 3. system. 4. The data transfer control system according to claim 3, wherein the identification information indicating the selected prefetch means is represented by using upper bits of the address that are not used in the address space of the memory. . 5. An address space of the memory is divided into a plurality of parts, and the prefetch means is provided for each divided space, and the identification means makes the prefetch means of the subspace to which a request address from the device belongs respond. 2. The data transfer control system according to claim 1, wherein: 6. The prefetch means stores a correspondence between the prefetch means selected by the device control means and a device corresponding to the prefetch means, and identifies the prefetch means corresponding to the device which has issued the read request from the correspondence relation. 2. The data transfer control system according to claim 1, wherein: 7. The device according to claim 1, wherein the identification unit identifies a device that has issued a read request based on a bus use permission signal issued by a bus arbiter, and identifies a prefetching unit corresponding to the device from the correspondence relationship. The data transfer control system according to claim 6. 8. The device control means sets a start address of the read processing for the selected prefetch means in addition to the prefetch method, and the selected prefetch means determines a prefetch method and a prefetch method from the device control means. 3. The data transfer control system according to claim 2, wherein when a start address is set, a prefetch process is started without waiting for a read request from the device. 9. A plurality of prefetch means are associated with one device, and a plurality of prefetch means can cope with a parallel access from the device to a plurality of different address ranges. Item 2. The data transfer control system according to Item 1. 10. A transfer control system for transferring data between a memory and a device, which can correspond to a plurality of prefetching methods, and prefetches data from the memory by a prefetching method designated therein. A plurality of read-ahead means for responding to the data of the address requested to be read from the device if the data is in the buffer, and device control means for controlling the device, A data transfer control system comprising: a device control unit configured to select and set a prefetch method corresponding to the read process to the prefetch unit when performing a read process from the memory. 11. An apparatus for controlling data transfer between a memory and a plurality of devices, wherein data is pre-read from the memory and stored in a buffer, and data at an address requested to be read from the device is stored in a buffer. A plurality of pre-reading means for responding to the data if it exists in the device; a means for receiving a selection of the pre-reading means used by the device for read processing from a device control means for controlling the device; A data transfer control device, comprising: identifying a prefetch means selected by the device control means for the device, and causing the prefetch means to respond to the read request.