JPH11104312A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To preclude the possibility that a display control means fails to take display control command data from a game control means when a power source is on. SOLUTION: In a game control board 31, an initial reset circuit 65 outputs a reset signal to a CPU 56. In a display control board 80, a reset circuit 83 outputs a reset signal to a display control CPU 91. A delay circuit 655 delays the reset signal from the initial reset circuit 65, and supplies it to the CPU 56.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a pachinko game machine,
For gaming machines such as coin gaming machines or slot machines,
In particular, the present invention relates to a gaming machine including a variable display device whose display state can be changed, and in which a predetermined game value can be given when a display result on the variable display device has a predetermined specific display mode.

[0002]

2. Description of the Related Art As a gaming machine, a variable display device having a variable display portion whose display state can be changed is provided, and when a display result of the variable display portion becomes a predetermined specific display mode, a predetermined game is performed. Some are configured to provide value to the player. The game value is a value of a variable winning prize ball device based on the result of a special game such as a symbol change in a special gaming device such as a variable display device provided in a gaming area of a gaming machine. To be in an advantageous state or to generate a right to be in an advantageous state for the player.

[0003] Some variable display devices have a plurality of variable display sections, and are usually configured to display the display results of the plurality of variable display sections at different times. On the variable display section, for example, a plurality of identification information such as symbols are variably displayed. The fact that the display result of the variable display unit is a combination of a predetermined specific display mode is usually referred to as a “big hit”.

[0004] In addition, among the combinations of the display modes of "outside" other than the combination of "big hit", at a stage where a part of the display results of the plurality of variable display portions has not been derived and displayed yet, the display results are already displayed. The state in which the display mode of the variable display unit that is derived and displayed satisfies the display condition that is a combination of the specific display modes is referred to as “reach”. A player plays a game while enjoying how to generate a jackpot.

In order to improve the taste of the game, the variable display device displays a background image and a character image in addition to the identification information. By displaying the background image related to the identification information and the character image, it is possible to further enhance the gaming effect for the player. Further, by performing display in which various characters perform various expressions at each stage when the identification information is variably displayed on the variable display section, a higher expectation can be given to the player.

The progress of the game in the gaming machine is controlled by game control means such as a microcomputer. The identification information, the character image, and the background image displayed on the variable display device are controlled by display control means operating according to display control command data from the game control means.
The identification information, the character image and the background image displayed on the variable display device generally include a display control microcomputer and data from the microcomputer in VRAM.
And a video display processor (VDP) for transferring the data of the VRAM to the variable display device side, but the display control microcomputer has a large program capacity. Therefore, the microcomputer of the game control means having a limited program capacity cannot control the identification information and the like displayed on the variable display device, and a microcomputer for display control is used.

[0007]

As described above, in the conventional gaming machine, display on the variable display device is controlled by display control means different from game control means. When each of the game control means and the display control means is constituted by a microcomputer, a reset circuit for initializing each microcomputer when the power is turned on is provided. The display control means receives the display control command data transmitted from the game control means, but if the reset signals from both reset circuits are not synchronized, the display control means will display the display transmitted from the game control means. Control command data may be missed. Therefore, a method has been proposed in which the microcomputers of the game control means and the display control means are reset by a common reset signal.

However, both microcomputers are
When the reset is released, the respective initialization programs are executed. Then, if the time during which the microcomputer of the display control means is executing the initialization program is longer than the time during which the microcomputer of the game control means is executing the initialization program, a common reset signal is used. However, there is a possibility that the display control command data is transmitted from the game control unit before the execution of the initialization program in the display control unit is completed. In such a case, the display control means misses the display control command data. That is, even if the microcomputers of the game control means and the display control means are reset by the common reset signal, there is a possibility that the display control means may fail to receive the display control command data from the game control means. Generally, the game control means and the display control means are configured on separate substrates. Therefore, in order to use a common reset signal, the reset signal must be wired between the substrates. In such a case, noise is likely to be added to the reset signal. Since the reset signal resets the microcomputer, if the reset signal contains noise, the microcomputer is reset during the progress of the game and the game is interrupted.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a gaming machine in which a display control means can reliably take in display control command data from a game control means while preventing a risk of noise on a reset signal. And

[0010]

A gaming machine according to the present invention comprises:
A gaming machine that includes a variable display device whose display state can be changed, and that can provide a predetermined game value when a display result of identification information displayed on the variable display device becomes a predetermined specific display mode. A microcomputer for game control for controlling the progress of the game, and a microcomputer for display control for controlling the display of the variable display device in response to a command from the microcomputer for game control; The power-on reset release timing of the microcomputer is earlier than the power-on reset release timing of the game control microcomputer. Gaming machines, for example,
An initial reset circuit for outputting a reset signal to the microcomputer for game control, a reset circuit for outputting a reset signal to the microcomputer for display control, and a game control circuit for delaying the reset signal from the initial reset circuit. A delay circuit for supplying to the microcomputer. An initial reset circuit for outputting a reset signal to the microcomputer for game control; and a reset circuit for outputting a reset signal to the microcomputer for display control, for generating a reset signal in the initial reset circuit. The capacity of the capacitor may be larger than the capacity of the capacitor for generating the reset signal in the reset circuit. When the microcomputer for game control executes a predetermined program such as a security check program when the power-on reset is released, an initial reset circuit for outputting a reset signal to the microcomputer for game control, and a microcomputer for display control And a reset circuit for outputting a reset signal to the reset circuit, and the initial reset circuit and the reset circuit may have the same configuration.

[0011]

An embodiment of the present invention will be described below with reference to the drawings. First, the overall configuration of a pachinko gaming machine, which is an example of a gaming machine, will be described. 1 is a front view of the pachinko gaming machine 1 as viewed from the front, FIG. 2 is an overall rear view showing the internal structure of the pachinko gaming machine 1, and FIG. 3 is a rear view of the pachinko gaming machine 1 as viewed from the back. Here, a pachinko gaming machine is shown as an example of a gaming machine, but the present invention is not limited to a pachinko gaming machine, and may be, for example, a coin gaming machine or a slot machine.

As shown in FIG. 1, the pachinko gaming machine 1 comprises:
It has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2, there is a hit ball supply tray 3. Below the hitting ball supply tray 3, a surplus ball receiving tray 4 for storing premium balls overflowing from the hitting ball supply tray 3 and a hitting operation handle 5 for firing a hitting ball are provided. A game board 6 is detachably mounted behind the glass door frame 2. A game area 7 is provided on the front of the game board 6.

In the vicinity of the center of the game area 7, an image display section 9 for variably displaying a plurality of types of symbols and a 7 segment L
A variable display device 8 including a variable display 10 using an ED is provided. In the image display section 9, "left", "middle",
There are three "right" symbol display areas 9a, 9b, 9c, and these symbol display areas 9a, 9b, 9c constitute variable display sections. On the side of the variable display device 8, a passing gate 11 for guiding a hit ball is provided. Passage gate 11
Is passed through the ball exit 13 to the starting winning opening 14. In a passage between the passage gate 11 and the ball outlet 13, there is a gate sensor 12 that detects a hit ball that has passed through the passage gate 11. The winning ball that has entered the starting winning port 14 is guided to the back of the game board 6 and detected by the starting port sensor 17. In addition, a variable winning ball device 15 that performs opening and closing operations is provided below the starting winning port 14. The variable winning ball device 15 is opened by the solenoid 16. An opening / closing plate 20 that is opened by the solenoid 21 in a specific game state (big hit state) is provided below the variable winning ball device 15. Of the prize balls guided from the opening / closing plate 20 to the back of the game board 6, the prize balls entering one (V zone) are detected by the V count sensor 22, and the prize balls entering the other are detected by the count sensor 23. . At the lower portion of the variable display device 8, a starting winning storage display 18 having four display sections for displaying the number of winning balls entering the starting winning port 14 is provided. In this example, the start winning prize storage display 18 increases the number of lit display units by one each time there is a starting prize, with the upper limit being four. And
Each time the variable display of the image display unit 9 is started, the number of the lit display units is reduced by one.

The game board 6 is provided with a plurality of winning ports 19 and 24. Decorative lamps 25 are provided around the left and right sides of the game area 7 so as to blink during the game.
There is an out port 26 for absorbing a hit ball that does not win. In addition, two speakers 27 that emit sound effects are provided at upper left and right sides outside the game area 7. On the outer periphery of the game area 7, a game effect lamp / LED 28 is provided. In this example, a prize ball lamp 51 that is turned on when a prize ball is paid out is provided in the vicinity of one of the speakers 27, and a ball out lamp 52 that is turned on when a replenishment ball is out in the vicinity of the other speaker 27. Is provided. Furthermore, in FIG. 1, it is installed adjacent to the pachinko gaming table 1,
Also shown is a card unit 50 that enables lending of balls by inserting a prepaid card.

A hit ball fired from the hitting ball launching device enters the game area 7 through the hitting rail, and thereafter, the game area 7
Come down. When a hit ball passes through the passage gate 11 and is detected by the gate sensor 12, the number displayed on the variable display 10 changes to a continuously changing state. Further, when the hit ball enters the start winning opening 14 and is detected by the start opening sensor 17, the symbol in the image display section 9 starts rotating. The rotation of the image in the image display unit 9 stops when a certain time has elapsed. If the combination of images at the time of stop is a combination of big hit symbols, the state shifts to a big hit gaming state. That is, the opening and closing plate 2
0 is released until a predetermined time elapses or until a predetermined number (for example, 10) of hit balls is won. When a hit ball wins in the specific winning area while the opening and closing plate 20 is being opened and is detected by the V count sensor 22, a continuation right is generated and the opening and closing plate 20 is opened again. The generation of the continuation right is permitted a predetermined number of times (for example, 16 times).

If the combination of images in the image display unit 9 at the time of stoppage is a combination of big hit symbols with probability fluctuations and the symbol indicated by the variable display 10 is a predetermined symbol, then the variable winning ball is set. The device 15 is frequently opened and the probability of the next big hit increases.
That is, the state becomes more advantageous for the player.

Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG. On the back of the variable display device 8, as shown in FIG. 2, a prize ball tank 38 is provided above the mechanism plate 36, and when the pachinko gaming machine 1 is installed on the gaming machine installation island, a prize ball is provided from above. Premium ball tank 3
8 is supplied. The prize ball in the prize ball tank 38 reaches the ball payout device through the guide gutter 39.

The mechanism board 36 includes a variable display control unit 29 for controlling the image display device 9 via the relay board 30, a game control board 31 covered with a board case 32 and mounted with a game control microcomputer, and the like. A relay board 33 for relaying a signal between the display control unit 29 and the game control board 31, and a prize ball board 37 on which a payout control microcomputer for performing payout control of a prize ball is mounted.
Is installed. Further, the mechanism plate 36 includes a hitting ball firing device 34 for shooting a hitting ball into the game area 7 by using the rotational force of a motor, a speaker 27 and a game effect lamp / LE.
An illumination board 35 for sending a signal to D28 is provided.

As shown in FIG. 3, on the back surface of the game board 6, there is provided a prize ball collecting cover 40 for guiding a prize ball that has won each prize port and a prize ball device along a predetermined prize path. I have. Out of the winning balls guided to the winning ball collecting cover 40, those winning through the opening / closing plate 20 are the ball payout device 9
7 is controlled so as to pay out a relatively large number of prize balls (for example, 15). The winnings through the starting winning opening 14 are controlled so that a ball payout device (not shown in FIG. 3) pays out a relatively small number of prize balls (for example, six). Then, the winnings through the other winning ports 24 and the winning ball device are controlled so that the ball payout device pays out a relatively medium number of prize balls (for example, 10). In order to perform such control, signals from the starting port sensor 17, the V count sensor 22, and the count sensor 23 are sent to the game control board 31. When a signal from each sensor is sent to the game control board 31, a prize ball number signal described later is sent from the game control board 31 to the prize ball board 37.

FIG. 4 shows a game control board (main board) 31.
FIG. 3 is a block diagram showing an example of a circuit configuration in FIG. FIG. 4 also shows a prize ball substrate 37, an illuminated substrate 35, and a display control substrate (sub-substrate) 80. The main board 31 includes a basic circuit 53 for controlling the pachinko gaming machine 1 according to a program, a gate sensor 12, a starting port sensor 17, a V count sensor 22, and a count sensor 23.
Circuit 58 for applying a signal from
And a solenoid 16 for opening and closing the variable winning ball device 15 and a solenoid 21 for opening and closing the opening and closing plate 20.
A solenoid circuit 59 driven in accordance with a command from
A lamp / LED circuit 6 for driving the variable indicator 10 using segmented LEDs and blinking the decorative lamp 25
0 and a prize ball substrate input / output circuit 61 for transmitting the prize ball number signal from the basic circuit 53 to the prize ball substrate 37 and for inputting the winning data signal from the prize ball substrate 37 to the basic circuit 53. . Prize winning detector 99
In this case, the winning ball substrate 37 outputs a winning data signal. The basic circuit 53 gives a prize ball number signal to the prize ball substrate 37 in accordance with a winning data signal from the prize ball substrate 37. For example, when the basic circuit 53 receives a winning data signal corresponding to the turning on of the starting port sensor 17,
"6" is output as the prize ball number signal, and when a winning data signal corresponding to the turning on of the count sensor 23 or the V count sensor 22 is input, "15" is output as the prize ball number signal. Then, when a winning data signal is input when these sensors are not turned on, "10" is output as the winning ball number signal.

The main board 31 includes an illuminated board 35.
Illuminated board command output circuit 62 for transmitting a command from the basic circuit 53 to the sub-board 80, and a display device circuit 63 for applying a command from the basic circuit 53 and a strobe signal to the sub-board 80
According to data provided from the basic circuit 53, jackpot information indicating occurrence of a jackpot, effective start information indicating the number of start winning balls used for starting image display on the image display unit 9, and indicating that a probability change has occurred. An information output circuit 64 that outputs probability change information and the like to a host computer such as a hall management computer; and a voice synthesis circuit 71 that outputs a sound signal such as a sound effect according to a control signal from the basic circuit 53.
And a volume amplification circuit 72 that amplifies the audio signal from the audio synthesis circuit 71 and provides the amplified signal to the speaker 27 shown in FIG.

The basic circuit 53 includes a ROM 54 for storing a game control program and the like, a RAM 55 used as a work memory, a CPU 56 for performing a control operation in accordance with the control program, and an I / O port unit 57. The RAM 55 may be built in the CPU 56 in some cases.

Further, the main board 31 is provided with an initial reset circuit 65 for resetting the basic circuit 53 when the power is turned on, and a reset pulse is given to the basic circuit 53 periodically (for example, every 2 ms) to control the game. A periodic reset circuit 66 for executing the program again from the beginning;
An address decode circuit 67 that decodes an address signal provided from the basic circuit 53 and outputs a signal for selecting one of the I / O ports in the I / O port unit 57 is provided.

FIG. 5 shows the circuit in the sub-board 80 and the CRT 8
2 is a block diagram illustrating a configuration of an image display unit 9 according to the first embodiment.
The sub-board 80 includes a reset circuit 83 for resetting the CRT control circuit 81, an oscillation circuit 84 for supplying a clock signal to the CRT control circuit 81,
And a VRAM 86 for storing image data generated by the T control circuit 81. A character ROM for storing frequently used image data may be provided. The frequently used image data is, for example, CR
The image includes a person, an animal, or a character, a graphic, a symbol, or the like displayed on T82.

When a strobe signal is input from the display device circuit 63 of the main board 31, the CRT control circuit 81 inputs display control command data from the display device circuit 63 and recognizes the state indicated by the command data.
The CRT control circuit 81 generates image data to be displayed on the CRT 82 according to the state of the display control command data. Then, the image data is stored in the VRAM 86. The image data stored in the VRAM 86 is RG
As a video signal composed of a B color signal and a SYNC signal,
The image is transmitted to the RT 82, and an image is displayed on the CRT 82.

FIG. 6 is a block diagram showing an example of the configuration of the CRT control circuit 81. The CRT control circuit 81 includes a display control CPU 91, a control data ROM 92 storing a display control program, video display processors 93 and 94, and a video color encoder 95. The display control CPU 91 analyzes display control command data from the display device circuit 63 in accordance with the display control program in the control data ROM 92. Then, the display control CPU 91 creates image data based on the display control command data, and transfers the image data to the VRAM 86 via the video controllers 93 and 94. The image data stored in the RAM 86 is synchronized with a synchronization signal from the color video encoder 95,
The video data is transferred from the video controllers 93 and 94 to the color video encoder 95. Color video encoder 95
Converts the image data into a video signal and sends it to the CRT 82. In addition, although not shown in FIG.
0 and CRT 82, C
CR having CRT drive circuit for driving RT82
A T substrate is provided. In this gaming machine, since two VDPs 93 and 94 are provided, symbols, backgrounds, and character information can be easily superimposed and displayed.

FIG. 7 is a timing chart showing transmission timing of display control command data. Each display control data constituting the display control command data is transmitted continuously, but as shown in FIG. 7, the display control data is transmitted every 2 ms. Then, a strobe signal is output in synchronization with each display control data. The display control CPU 91 includes:
Since an interrupt occurs at the rising edge of the strobe signal, the display control CPU 91 can fetch each display control data by the interrupt processing program.

FIG. 8 shows the main board 31 and the sub board 8.
0 initial reset circuit 65 and reset circuit 8
FIG. 3 is a circuit diagram showing a periphery of the circuit No. 3; In this embodiment, in the initial reset circuit 65 and the reset circuit 83,
The same reset ICs 651 and 831 are used. When the input potential of the predetermined terminal exceeds a predetermined value (for example, 3 V), the reset ICs 651 and 831 change the output level of the RESET # terminal from a low level to a high level. Therefore, the reset IC 651 in the initial reset circuit 65
Are connected to a resistor 652 and a capacitor 653 which are pulled up to a power supply. The other end of the capacitor 653 is grounded. Further, a resistor 832 and a capacitor 833 that are pulled up to a power supply are connected to predetermined terminals of a reset IC 831 in the reset circuit 83. The other end of the capacitor 653 is grounded. Note that the resistance value of the resistor 652 is equal to the resistance value of the resistor 832, for example, 470 k
Ω is used. The capacity of the capacitor 653 is equal to the capacity of the capacitor 833, for example, 1000
The one with pF is used. Therefore, when the game machine is powered on, the reset IC in the initial reset circuit 65 is reset.
The output level of the RESET # terminal 651 and the output level of the RESET # terminal of the reset IC 831 in the reset circuit 83 change to the high level almost simultaneously.

A delay circuit 655 is provided between the initial reset circuit 65 and the CPU 56 on the main board 31. The delay circuit 655 is connected to the reset IC 651
The output of the SET # terminal is delayed and supplied to the reset input terminal (RST # terminal) of the CPU 56.

FIG. 8 shows an output port 571 for transmitting display control command data and another output port 572.
575 are also shown. In addition, the output ports 571-5
Reference numeral 75 denotes a part of the I / O port unit 57 shown in FIG. Output ports 571 to 575 are reset input terminals (R
ST￣ terminal), and a signal obtained by further delaying the output of the delay circuit 655 by two Schmitt trigger inverting circuits (hereinafter simply referred to as inverting circuits) 656 and 657 is supplied to the reset input terminal.

As shown in FIG. 8, the display control command data is output from the output port 571 of the I / O port unit 57 in the basic circuit 53. Also, the output port 571
A strobe signal is output from output port 572 in synchronization with the output from. The strobe signal is a display control CP.
The signal is input to an IRQ2 terminal which is an interrupt input terminal of U91. Therefore, the display control CPU 91 can know that the display control command data has been transmitted in response to the interrupt request of the IRQ2 terminal. The display control command data is input to a built-in input port of the display control CPU 91. In the interrupt control program in the display control program, display control command data input to the input port is fetched and stored. The display device circuit 63
Is for amplifying current of the display control command data and the strobe signal. FIG. 9 is a timing chart showing a signal example of a main part in the circuit shown in FIG.

Next, the operation will be described. When the power of the pachinko gaming machine 1 is turned on, the capacitor 653 is charged via the resistor 652 in the initial reset circuit 65 of the main board 31. Therefore, the potential of the capacitor 653 increases. When the potential of the capacitor 653 exceeds a predetermined value, as shown in FIG.
Changes the output level of the RESET terminal from the low level to the high level (at the timing A). The delay circuit 655 delays the output of the RESET # terminal of the reset IC 651 and supplies it to the CPU 56 as a reset signal. Therefore, as shown in FIG. 9, a low-level reset signal is supplied to the CPU 56 until a timing B that is later than the timing A after the power is turned on, and the reset signal rises to a high level at the timing B. That is, the reset of the CPU 56 is released at the timing B. The amount of delay in the delay circuit 655 is
For example, the amount is set such that the display control command data is not transmitted from the game control means before the execution of the initialization program of the display control CPU 91 is completed.

When the pachinko gaming machine 1 is powered on,
In the sub-substrate 80, the capacitor 83 is connected via the resistor 832.
3 is being charged. Therefore, the potential of the capacitor 833 increases. The reset IC 831 is the reset IC 6
51, the resistance of the resistor 832 is equal to the resistance of the resistor 652, and the capacitance of the capacitor 833 is equal to the capacitance of the capacitor 653.
Changes the output level of the RESET # terminal from a low level to a high level substantially at the timing A. In the sub-board 80, the RESET terminal is a direct display control CP.
Since it is connected to the reset input terminal of U91, FIG.
As shown in FIG.
Reset is released at the point of.

The signals input to the reset input terminals of the output ports 571 to 575 on the main board 31 are low by the inverting circuits 656 and 657 from the timing B to the timing C slightly delayed as shown in FIG. Level (reset state). Therefore, C
Output port 571 before PU56 reset is released
No. 575 does not output illegal data.

When the reset of the CPU 56 is released, C
The PU 56 executes a process as shown in the flowchart of FIG. As described above, this processing is performed by a reset pulse generated by the periodic reset circuit 66, for example, by 2 m.
It is started every s. When the CPU 56 is started, first,
A stack setting process for setting the designated address of the stack pointer is performed (step S1). Next, an initialization process is performed (step S2). In the initialization process, C
The PU 56 determines whether an error is included in the RAM 55, and if an error is included, performs processing such as initializing the RAM 55. Then, after performing a process of setting the display control command code sent to the sub-board 80 in a predetermined area of the RAM 55 (step S3), a process of outputting the command code via the output port 571 is performed (step S4). . Steps S1 and S2
Is executed only once after the above-mentioned initial reset is released.

Next, a process for transmitting a predetermined command for LED lighting control to the illuminated board 35 via the output port and the illuminated board command output circuit 62 is performed. Then, a process for transmitting data such as jackpot information, start information, and probability variation information to the hall management computer is performed (data output process: step S5). In addition, various abnormality diagnosis processes are performed by the self-diagnosis function provided inside the pachinko gaming machine 1, and an alarm is issued if necessary according to the result (error process: step S6).

Next, processing for updating each counter indicating each random number for determination is performed (step S7). In step S7, the CPU 56 counts up (addition of 1) the jackpot determination random number for determining whether or not to make a jackpot and the specific symbol determination random number for determining the combination of symbols at the time of the jackpot. That is, they are the random numbers for determination.

Next, the CPU 56 performs a special symbol process (step S8). In the special symbol process control, a corresponding process is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to a gaming state. Then, the value of the special symbol process flag is updated during each processing according to the gaming state. In the special symbol process, the CPU
56 outputs a control signal to the solenoids 16 and 21 at a predetermined timing via an output port and a solenoid circuit 59, and gives a control signal to the voice synthesis circuit 71 via the output port.

The CPU 56 performs a normal symbol process (step S9). In the normal symbol process process, a corresponding process is selected and executed according to a normal symbol process flag for controlling the variable display 10 using the 7-segment LED in a predetermined order. Then, the value of the normal symbol process flag is updated during each process according to the gaming state. Further, the CPU 56 controls the switch circuit 5
The state of the gate sensor 12, the starting port sensor 17, the count sensor 23, and the V count sensor 22 are input through the input port 8 and the input port, and it is determined whether or not there is a prize for each prize port or prize ball device (step S10). .

The CPU 56 further performs a process of updating the display random number (step S11). That is, count-up (1 addition) of a random number for determining a missing symbol and a reach determination random number for determining whether or not to reach is performed.

Further, the CPU 56 performs signal processing with the award ball substrate 37 (step S12). The winning is detected by the winning ball detector 99. In this case, the winning ball substrate 37 outputs a winning data signal. CPU56
Input the winning data signal through the input port,
The number of winning balls according to the ON / OFF state of each sensor confirmed in step S10 is determined, and the determined result is output to the winning ball substrate 37 via the output port and the winning ball substrate input / output circuit 61 as a winning ball number signal. I do. The payout control microcomputer mounted on the prize ball board 37 drives the ball payout device 97 according to the prize ball number signal.

Thereafter, the CPU 56 repeats the display random number updating process in step S13 until the next reset pulse is given from the periodic reset circuit 66. That is,
One is added to the value of each random number.

Then, in accordance with the processing of each of the above steps, the module that performs the processing of transmitting the display control command data in the game control program outputs the corresponding display control command data to the output port 571,
A strobe signal is output to output port 572.

On the sub-board 80, a display control CPU
When the reset of the CPU 91 is released, the display control CPU 91
Starts operation. When the operation starts, the display control CP
U91 first performs an initialization process as shown in the flowchart of FIG. In the initialization process, first, V
Processing for initializing the internal registers of the DPs 93 and 94 is performed (step S401).

In the VDP register initialization process, the image display unit 9 performs a process of writing set values to the internal registers of the VDPs 93 and 94 so that an image is displayed at a predetermined position determined in the gaming machine. . Also, V
A predetermined value is written to an internal register to set the operation mode of DPs 93 and 94.

When the VDP register initialization processing ends, the display control CPU 91 performs processing for initializing the built-in work RAM (step S402). When the execution of the initialization processing including the VDP register initialization processing and the work RAM initialization processing is completed, the display control CPU 91
Executes the main program (the process of step S403) of the process shown in the flowchart of FIG.
In this embodiment, the main program is executed using IRQ1 interrupt as a basic cycle. The IRQ1 interrupt is generated from VDP93 or VDP94 as shown in FIG. In this embodiment, IRQ1 interrupt is 1
Occurs every / 60 seconds. 1/60 second is the same as the cycle of VSYNC. By setting 1/60 seconds as the basic cycle, it is possible to update the display content in synchronization with VSYNC, and as a result, it is possible to prevent the screen from flickering.

More specifically, an interrupt occurrence flag is set in the IRQ1 interrupt processing program, and the process starts when the interrupt occurrence flag is set in the main program (step S403). In the main program, first, a watchdog timer setting process is performed (step S404). The reset circuit 83 shown in FIG. 8 also has a watchdog timer function. That is, CL
If no clock signal is input to the K terminal for a predetermined time or more, the reset circuit 83 outputs a reset signal to the display control CPU 91. This predetermined time is 1/60
Set to a number of seconds. Display control CPU 91
Supplies a pulse signal to the reset circuit 83 from a predetermined output port in the watchdog timer setting process. If the IRQ1 interrupt continues to be generated normally from the VDPs 93 and 94 and the display control CPU 91 continues to operate normally, the watchdog timer setting process is executed every 1/60 second. No signal is generated.

When the IRQ1 interrupt stops from the VDPs 93 and 94 or the display control CPU 91 goes out of control, the watchdog timer setting process is not executed.
Then, a reset signal is output from the reset circuit 83 after a lapse of a predetermined time. The reset signal resets the display control CPU 91 and executes the initialization process, so that the display control CPU 91 and the VDP 9
3, 94 can be restored to the normal state.

After the watchdog timer setting process, the display control CPU 91 analyzes the display control command data (step S405), and according to the received display control command data and the internal state as follows. Process. The display control command data is received by the display control CPU 91 through the IRQ2 interrupt processing, and is stored in a predetermined RAM area.

Demonstration screen display processing (step S500): The character data for the demonstration screen is transferred to the VRAM 86 via the VDPs 93 and 94, and the necessary image data (background image, etc.)
The data is transferred to the VRAM 86 via DPs 93 and 94. The demonstration screen display processing is performed in response to a demonstration display command which is command data for display control from the main board 31. The basic circuit 53 in the main board 31 outputs a demonstration display command when no prize has been won for a predetermined time (for example, 30 seconds). The case where there is no prize for a predetermined time or more generally means the case where no game is played.

Big hit display processing (step S501):
The big hit display screen is drawn on the VRAM 86. Big hit symbol display processing (step S502): The big hit symbol is drawn in the VRAM 86. Processing during opening of the special winning opening (step S503): The effect screen during opening of the special winning opening is drawn in the VRAM 86. Further, the special winning opening opening round number and the effect screen corresponding to the round number are drawn in the VRAM 86. Further, a specific area passage display is drawn in the VRAM 86.

Reach start processing (step S504):
Reach character data via VDP93, 94
The image data is transferred to the RAM 86 and the necessary image data (such as a background image) is transferred to the VRAM 86 via the VDPs 93 and 94. Further, the symbol display data is transferred to the VRAM 86. Reach processing (step S505): The symbol display data is set to V
The data is transferred to the VRAM 86 via DPs 93 and 94. Normal symbol display screen processing (step S506): The normal symbol display data is transferred to the VRAM via the VDPs 93 and 94.
86.

All symbol variation display processing (step S50)
7): The symbol display data in which all symbols fluctuate is stored in VRAM.
86. Left symbol stop start display processing (step S508): The symbol two symbols before the left symbol to be finally stopped is transferred to the VRAM 86. After that, the left symbol display data which fluctuates at a predetermined speed is transferred to the VRAM 86. Left symbol stop display processing (step S509): The left symbol is transferred to the VRAM 86. Right symbol stop start display processing (step S510): The symbol two symbols before the right symbol to be finally stopped is transferred to the VRAM 86. Thereafter, the right symbol display data, which fluctuates at a predetermined speed, is transferred to the VRAM 86. Right symbol stop display process (step S511): The right symbol is transferred to the VRAM 86. Middle symbol stop start display processing (step S512): The symbol two symbols before the middle symbol to be finally stopped is transferred to the VRAM 86. After that, the middle symbol display data which fluctuates at a predetermined speed is transferred to the VRAM 86. All symbols stop display processing (step S513): The stopped symbols are transferred to the VRAM 86.

When any of the above processes is executed, the display control CPU 91 enters a state of waiting for an IRQ1 interrupt.
Note that the processing of steps S500 to S513 shown in FIG. 11 is an example, and more processing may be performed in accordance with variations of the game effect prepared for the gaming machine. For example, a symbol pause process may be added. The image data drawn on the VRAM 86 is synchronized with HSYNC and VSYNC in VD
The data is transferred from P93 and 94 to the video color encoder 96. The video color encoder 96 converts the image data into R
The signal is converted to a GB video signal and output to the CRT 82 side.

In this embodiment, by providing the delay circuit 655, when the pachinko gaming machine 1 is powered on, the display control CPU 9 constituting the display control means is provided.
1 is set to be earlier than the reset release timing of the CPU 56 constituting the game control means, so that the execution of the initialization program in the display control means is not completed before the display control command is issued from the game control means. It does not occur that the data is transmitted and the display control means fails to receive the display control command data.

FIG. 12 is a circuit diagram showing another embodiment of the initial reset circuit 65 and the reset circuit 83 in the main board 31 and the sub board 80 in the gaming machine according to the present invention. In this embodiment, the delay circuit 655 is not provided. The output of the initial reset circuit 65 is directly connected to the reset input terminal of the CPU 56.
However, the capacity of the capacitor 654 in the initial reset circuit 65 of the main board 31 is larger than the capacity of the capacitor 833 in the reset circuit of the sub board 80. When the pachinko gaming machine 1 is powered on, the capacitor 65
4,833, the charging of which starts, but the degree of increase in the potential of the capacitor 654 is smaller than the degree of increase in the potential of the capacitor 833. Therefore, the potential of the capacitor 833 reaches the predetermined value earlier. Then, as shown in FIG. 13, the output of the RESET # terminal of the reset circuit 83, that is, the reset signal given to the display control CPU 91 rises earlier. Therefore, the display control CPU 91
Is reset earlier than the CPU 56 of the main board 31.

In this embodiment, the main substrate 3
1, the reset input terminals of the output ports 571 to 575 are at a low level (reset state) from timing B to timing C, which is slightly delayed, as shown in FIG. Therefore, no illegal data is output from the output ports 571 to 575 before the reset of the CPU 56 is released.

As described above, also in this embodiment, when the game machine is powered on, the reset release timing of the display control CPU 91 constituting the display control means is set to
Since the timing of reset release of the CPU 56 constituting the game control means is set earlier, display control command data is sent from the game control means before the execution of the initialization program in the display control means is completed, and the display control means Does not miss the display control command data. Further, in this embodiment, since it is not necessary to use the delay circuit 655, the circuit configuration is simplified.

The CPU 56 of the main board 31 may be configured to execute a predetermined security check program prior to the game control program after the reset is released. If it takes a certain time to execute the security check program, the reset release of the display control CPU 91 of the sub-board 80 can be expedited by using the time. FIG. 14 is a circuit diagram showing still another embodiment based on such a concept.

Also in this case, the delay circuit 655 is not provided, and the output of the initial reset
6 reset input terminal. The capacity of the capacitor 653 in the main board 31 is
It may be the same as the capacitance of the capacitor 833 at 0. Therefore, as shown in FIG.
And the display control CPU 91 of the sub-board 80 are reset almost simultaneously (at the timing A). CPU
When the reset is released, the security check program 56 first executes the security check program. While the security check program is being executed, the display control command data is not output from the CPU 56. If it takes a sufficient time to execute the security check program, the display control CPU 91 has finished executing the initialization program during that time. Therefore, it is in a state of waiting for a display control command.

In this embodiment, as shown in FIG. 15, the time when the execution of the security check program is completed is the substantial timing of reset release of the CPU 56. Therefore, also in this embodiment, after the power of the gaming machine is turned on, the reset release timing of the display control CPU 91 constituting the display control means is determined by the timing of C which constitutes the game control means.
This is substantially earlier than the reset release timing of the PU 56. Therefore, a situation does not occur in which the display control command data is sent from the game control means before the execution of the initialization program in the display control means is completed, and the display control means fails to receive the display control command data.

In this embodiment, as shown in FIG. 15, the same reset ICs 651 and 831 are used, the resistance values of the resistors 652 and 832 are made the same, and the capacitor 65
The configuration is such that both reset signals rise at approximately the same timing with the same capacitance of 3,833.
Even in the case where the PU 56 executes the security check program, the rise timing of the actual reset signal in the sub-board 80 may be set earlier as described in the above embodiment.

In each of the above-described embodiments, the case where the image display unit 9 using the CRT 82 for variably displaying symbols is used has been described. However, the case where a variable display device using an LCD is used may be used. Further, the present invention can be applied to a video-type pachinko gaming machine or a slot machine in which the board is entirely composed of video.

[0064]

As described above, according to the present invention, the power-on reset release timing of the display control microcomputer of the gaming machine is earlier than the power-on reset release timing of the game control microcomputer. With such a configuration, there is an effect that the display control command data can be reliably taken in by the display control means from the game control means. An initial reset circuit for outputting a reset signal to the microcomputer for game control, a reset circuit for outputting a reset signal to the microcomputer for display control, and a game control circuit for delaying the reset signal from the initial reset circuit. When a configuration including a delay circuit to be supplied to the microcomputer is used, the initial reset circuit and the reset circuit can have the same configuration. Further, when the capacity of the capacitor for generating the reset signal in the initial reset circuit is made larger than the capacity of the capacitor for generating the reset signal in the reset circuit, there is an effect that the circuit configuration is simplified. When the microcomputer for game control executes a predetermined program such as a security check program when the power-on reset is released, the initial reset circuit and the reset circuit can have the same configuration, and the circuit configuration is further simplified. Has an effect.

[Brief description of the drawings]

FIG. 1 is a front view of a pachinko gaming machine viewed from the front.

FIG. 2 is an overall rear view showing the internal structure of the pachinko gaming machine.

FIG. 3 is a rear view of the gaming board of the pachinko gaming machine as viewed from the rear.

FIG. 4 is a block diagram showing an example of a circuit configuration in the game control board.

FIG. 5 is a block diagram illustrating a circuit in a sub-board and a configuration of an image display unit using a CRT.

FIG. 6 is a block diagram illustrating an example of a configuration of a CRT control circuit.

FIG. 7 is a timing chart showing transmission timing of display control command data.

FIG. 8 is a circuit diagram showing the periphery of an initial reset circuit and a reset circuit on a main board and a sub board.

FIG. 9 is a timing chart showing an example of signals of main parts in the circuit shown in FIG. 8;

FIG. 10 is a flowchart showing the operation of the CPU on the main board.

FIG. 11 is a flowchart showing the operation of the display control CPU on the sub-board.

FIG. 12 is a circuit diagram showing another embodiment around the initial reset circuit and the reset circuit on the main board and the sub-board.

FIG. 13 is a timing chart showing an example of signals of a main part in the circuit shown in FIG. 12;

FIG. 14 is a circuit diagram showing still another embodiment around the initial reset circuit and the reset circuit on the main board and the sub board.

15 is a timing chart showing a signal example of a main part in the circuit shown in FIG. 14;

[Explanation of symbols]

 8 Variable Display 9 Image Display 31 Game Control Board (Main Board) 53 Basic Circuit 56 CPU 65 Initial Reset Circuit 80 Display Control Board (Sub Board) 83 Reset Circuit 91 Display Control CPUs 651, 831 Reset ICs 652, 832 Resistance 653, 654, 833 Capacitor 655 Delay circuit

Claims (4)

[Claims] 1. A variable display device whose display state is changeable, wherein a predetermined game value is given when a display result of identification information displayed on the variable display device has a predetermined specific display mode. A gaming machine which is capable of: a microcomputer for game control for controlling the progress of a game; and a microcomputer for display control for controlling display of the variable display device in response to a command from the microcomputer for game control. A gaming machine, comprising: a computer; and a power-on reset release timing of the display control microcomputer is earlier than a power-on reset release timing of the game control microcomputer. 2. An initial reset circuit for outputting a reset signal to a game control microcomputer, a reset circuit for outputting a reset signal to a display control microcomputer, and delaying a reset signal from the initial reset circuit. 2. The gaming machine according to claim 1, further comprising: a delay circuit for supplying the control signal to the game control microcomputer. 3. An initial reset circuit for outputting a reset signal to a game control microcomputer; and a reset circuit for outputting a reset signal to a display control microcomputer. 2. The gaming machine according to claim 1, wherein the capacity of the capacitor for creating is larger than the capacity of the capacitor for creating the reset signal in the reset circuit. 4. A microcomputer for game control,
An initial reset circuit for outputting a reset signal to the game control microcomputer; and a reset circuit for outputting a reset signal to the display control microcomputer. The gaming machine according to claim 1, further comprising: the initial reset circuit and the reset circuit having the same configuration.