JPH1147408A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely prevent unauthorized data from being output when the power is supplied to the machine by providing a control means and a reset means for resetting an interface means and releasing reset of the interface means after a designated period from reset releasing of the control means. SOLUTION: When the power is applied to a game machine, an electric current is applied to a main substrate by a power supply circuit 90, and a capacitor 653 is filled in a reset circuit 65, so that the potential between a resistance 652 and the capacitor 653, that is, the input voltage of a reset IC 651 is gradually increased. When the input voltage exceeds a designated value, the output of the reset IC 651 is changed from low to high, and the potential of a reset terminal of a CPU 65 becomes high after delay time after the application of voltage to the main substrate due to such a change of output, so that the CPU 56 is released from resetting to be put in the state of starting the operation. The output of the reset IC 651 is also input to reset terminals of the respective output ports 571-577 through a delay circuit 94.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gaming machine such as a pachinko gaming machine in which a control means such as a microprocessor sends and receives signals to and from peripheral circuits and peripheral devices via an interface means and controls the progress of the game.

[0002]

2. Description of the Related Art In a pachinko game machine, a predetermined number of prize balls or a value corresponding thereto is given when a hit ball fired by a player wins a predetermined winning opening or a winning ball device provided in a gaming area of a gaming board. The game proceeds as if paid out to the player. In addition, when a specific condition is satisfied, the state of the variable winning ball device may be in an advantageous state for a player who is likely to win a hit ball, or a right may be generated to be in an advantageous state for the player, It is configured to improve the taste of the game. Further, in order to enhance the game effect, a sound generating device that emits a predetermined sound effect, and a lamp or LED that performs a predetermined blinking are provided.

The progress of a game in a gaming machine is controlled by control means such as a microprocessor (hereinafter, referred to as a CPU). When the control means is realized by a CPU, control signals for the above-described sound generator, lamp, LED, and the like are output to them via interface means connected to a bus of the CPU, for example, an I / O port. . If the gaming machine is provided with a display device such as an LCD or a CRT, signals for these are also output via the interface means. Further, when the winning ball device is configured to be openable and closable, a signal given to a solenoid or the like for opening and closing such a variable winning ball device is also output via the interface means. Also,
Control signals from the CPU other than those described above are output via the interface means. For example, a signal mounted on a circuit board mounted on a board other than the board mounted with the CPU or a signal to a device external to the gaming machine such as a hall computer is also output via the interface means.

[0004]

In such a gaming machine, an abnormal signal is output from the interface means due to noise generated when the power is turned on or the like, and an abnormal sound is generated from a speaker or an LED is generated. Or the lamp may be turned on abnormally. Further, due to the noise, a solenoid or the like that opens and closes the variable winning ball device may be driven and a game may be started with the variable winning ball device being opened. Further, erroneous information may be output to a device outside the gaming machine such as a hall computer due to the noise.

The present invention has been made in order to avoid such a problem, and it is possible to reliably avoid abnormal operation of a speaker, a lamp, an LED, a variable winning prize ball device, and the like of a game machine, and to control the game machine. An object of the present invention is to provide a gaming machine that can reliably prevent an abnormal signal from being output to a device mounted on a board other than the board on which the board is mounted or a device external to the gaming machine, such as a hall computer. I do.

[0006]

A gaming machine according to the present invention comprises:
A special prize port such as a start winning prize port where a game ball can be won and a special game device such as a variable display device for performing a predetermined special game when a game ball wins a specific prize port are provided on the game board, A game machine capable of giving a game value to a player based on a result of a special game, a control means for controlling the progress of the game, a plurality of interface means for receiving and outputting a control signal from the control means, Reset means for resetting the means and the interface means and releasing the reset of the interface means after a predetermined period from the reset release of the control means. The game value is a state in which the state of the variable prize ball device is advantageous for a player who is likely to win a ball based on the result of a special game such as a symbol change in a special game device provided in the game area of the gaming machine. Or to generate the right to be in an advantageous state for the player. Further, the predetermined period is a period that is equal to or longer than a period from the reset release of the control unit to the stabilization of the output of the control unit. The reset unit may be configured to include a control reset unit that resets the control unit, and a delay unit that delays the output of the control reset unit and provides the output to the interface unit. For example, the interface means is a solenoid circuit for driving a variable winning ball device, a display such as a variable display and a display drive circuit for driving a lighting element such as a lamp or an LED,
In addition, a control signal is output to a sound generation unit that generates sound.

[0007]

An embodiment of the present invention will be described below with reference to the drawings. First, the overall configuration of a pachinko gaming machine, which is an example of a gaming machine, will be described. 1 is a front view of the pachinko gaming machine 1 as viewed from the front, FIG. 2 is an overall rear view showing the internal structure of the pachinko gaming machine 1, and FIG. 3 is a rear view of the pachinko gaming machine 1 as viewed from the back. Here, a pachinko gaming machine is shown as an example of a gaming machine, but the present invention is not limited to a pachinko gaming machine, and may be, for example, a coin gaming machine or a slot machine.

As shown in FIG. 1, the pachinko gaming machine 1 comprises:
It has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2, there is a hit ball supply tray 3. Below the hitting ball supply tray 3, a surplus ball receiving tray 4 for storing premium balls overflowing from the hitting ball supply tray 3 and a hitting operation handle 5 for firing a hitting ball are provided. A game board 6 is detachably mounted behind the glass door frame 2. A game area 7 is provided on the front of the game board 6.

In the vicinity of the center of the game area 7, an image display section 9 for variably displaying a plurality of types of symbols and a 7 segment L
A variable display device 8 including a variable display 10 using an ED is provided. In the image display section 9, "left", "middle",
There are three "right" symbol display areas 9a, 9b, 9c, and these symbol display areas 9a, 9b, 9c constitute variable display sections. On the side of the variable display device 8, a passing gate 11 for guiding a hit ball is provided. Passage gate 11
Is passed through the ball exit 13 to the starting winning opening 14. In a passage between the passage gate 11 and the ball outlet 13, there is a gate sensor 12 that detects a hit ball that has passed through the passage gate 11. The winning ball that has entered the starting winning port 14 is guided to the back of the game board 6 and detected by the starting port sensor 17. In addition, a variable winning ball device 15 that performs opening and closing operations is provided below the starting winning port 14. The variable winning ball device 15 is opened by the solenoid 16. An opening / closing plate 20 that is opened by the solenoid 21 in a specific game state (big hit state) is provided below the variable winning ball device 15. Of the prize balls guided from the opening / closing plate 20 to the back of the game board 6, the prize balls entering one (V zone) are detected by the V count sensor 22, and the prize balls entering the other are detected by the count sensor 23. . At the lower portion of the variable display device 8, a starting winning storage display 18 having four display sections for displaying the number of winning balls entering the starting winning port 14 is provided. In this example, the start winning prize storage display 18 increases the number of lit display units by one each time there is a starting prize, with the upper limit being four. And
Each time the variable display of the image display unit 9 is started, the number of the lit display units is reduced by one.

The game board 6 is provided with a plurality of winning ports 19 and 24. Decorative lamps 25 are provided around the left and right sides of the game area 7 so as to blink during the game.
There is an out port 26 for absorbing a hit ball that does not win. In addition, two speakers 27 that emit sound effects are provided at upper left and right sides outside the game area 7. On the outer periphery of the game area 7, a game effect lamp / LED 28 is provided. In this example, a prize ball lamp 51 that is turned on when a prize ball is paid out is provided in the vicinity of one of the speakers 27, and a ball out lamp 52 that is turned on when a replenishment ball is out in the vicinity of the other speaker 27. Is provided. Furthermore, in FIG. 1, it is installed adjacent to the pachinko gaming table 1,
Also shown is a card unit 50 that enables lending of balls by inserting a prepaid card.

[0011] The hit ball fired from the hitting ball launching device enters the game area 7 through the hitting rail, and thereafter enters the game area 7.
Come down. When a hit ball passes through the passage gate 11 and is detected by the gate sensor 12, the number displayed on the variable display 10 changes to a continuously changing state. Further, when the hit ball enters the start winning opening 14 and is detected by the start opening sensor 17, the symbol in the image display section 9 starts rotating. The rotation of the image in the image display unit 9 stops when a certain time has elapsed. If the combination of images at the time of stop is a combination of big hit symbols, the state shifts to a big hit gaming state. That is, the opening and closing plate 2
0 is released until a predetermined time elapses or until a predetermined number (for example, 10) of hit balls is won. When a hit ball wins in the specific winning area while the opening and closing plate 20 is being opened and is detected by the V count sensor 22, a continuation right is generated and the opening and closing plate 20 is opened again. The generation of the continuation right is permitted a predetermined number of times (for example, 16 times).

If the combination of images in the image display unit 9 at the time of stoppage is a combination of big hit symbols with probability fluctuations and the symbol shown on the variable display 10 is a predetermined symbol, then the variable winning ball is set. The device 15 is frequently opened and the probability of the next big hit increases.
That is, the state becomes more advantageous for the player.

Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG. On the back of the variable display device 8, as shown in FIG. 2, a prize ball tank 38 is provided above the mechanism plate 36, and when the pachinko gaming machine 1 is installed on the gaming machine installation island, a prize ball is provided from above. Premium ball tank 3
8 is supplied. The prize ball in the prize ball tank 38 reaches the ball payout device through the guide gutter 39.

The mechanism board 36 includes a variable display control unit 29 for controlling the image display device 9 via the relay board 30, a game control board 31 covered with a board case 32 and mounted with a game control microcomputer, etc. A relay board 33 for relaying a signal between the display control unit 29 and the game control board 31, and a prize ball board 37 on which a payout control microcomputer for performing payout control of a prize ball is mounted.
Is installed. Further, the mechanism plate 36 includes a hitting ball firing device 34 for shooting a hitting ball into the game area 7 by using the rotational force of a motor, a speaker 27 and a game effect lamp / LE.
An illumination board 35 for sending a signal to D28 is provided.

As shown in FIG. 3, on the rear surface of the game board 6, there is provided a winning ball set cover 40 for guiding the winning balls which have won the winning holes and the winning ball device along a predetermined winning route. I have. Out of the winning balls guided to the winning ball collecting cover 40, those winning through the opening / closing plate 20 are the ball payout device 9
7 is controlled so as to pay out a relatively large number of prize balls (for example, 15). The winnings through the starting winning opening 14 are controlled so that a ball payout device (not shown in FIG. 3) pays out a relatively small number of prize balls (for example, six). Then, the winnings through the other winning ports 24 and the winning ball device are controlled so that the ball payout device pays out a relatively medium number of prize balls (for example, 10). In order to perform such control, signals from the starting port sensor 17, the V count sensor 22, and the count sensor 23 are sent to the game control board 31. When a signal from each sensor is sent to the game control board 31, a prize ball number signal described later is sent from the game control board 31 to the prize ball board 37.

FIG. 4 shows a game control board (main board) 31.
FIG. 3 is a block diagram showing an example of a circuit configuration in FIG. FIG. 4 also shows a prize ball substrate 37, an illuminated substrate 35, and a display control substrate 80. The main board 31 includes a basic circuit 53 that controls the pachinko gaming machine 1 according to a program, a switch circuit 58 that supplies signals from the gate sensor 12, the starting port sensor 17, the V count sensor 22, and the count sensor 23 to the basic circuit 53. A solenoid circuit 59 for driving a solenoid 16 for opening and closing the variable winning ball device 15 and a solenoid 21 for opening and closing the opening and closing plate 20 in accordance with a command from the basic circuit 53;
D, a lamp / LED circuit 60 for driving the variable display 10 and blinking the decoration lamp 25; a command from the basic circuit 53 to the prize ball substrate 37; and a prize data signal from the prize ball substrate 37. A prize ball substrate input / output circuit 61 for inputting to 53 is provided. The basic circuit 53 gives a prize ball number signal to the prize ball substrate 37 in accordance with a winning data signal from the prize ball substrate 37. For example,
The basic circuit 53 outputs “6” to the prize ball number signal when the winning data signal corresponding to the turning on of the starting port sensor 17 is input, and the count sensor 23 or the V count sensor 2
When a winning data signal corresponding to turning on of 2 is input, "15" is output as the winning ball number signal. Then, when a winning data signal is input when these sensors are not turned on, "10" is output as the winning ball number signal. The main board 31 also includes an illuminated board command output circuit 62 for transmitting a command from the basic circuit 53 to the illuminated board 35,
A CRT circuit 63 for giving a command or a strobe signal from the basic circuit 53 to the image display unit 9 based on T;
According to the data given from 3, the jackpot information indicating the occurrence of the jackpot, the effective start information indicating the number of start winning balls used to start the image display of the image display unit 9, the probability change information indicating that the probability variation has occurred, and the like. An information output circuit 64 for outputting to a host computer such as a hall management computer, a speech synthesis circuit 71 for outputting a sound signal such as a sound effect according to a control signal from the basic circuit 53, and a sound from the speech synthesis circuit 71 A volume amplifying circuit 72 for amplifying a signal and supplying the amplified signal to the speaker 27 shown in FIG. 1 is provided.

Here, the display drive circuit for driving the display and the lighting element is composed of a lamp / LED circuit 60, an illuminated board command output circuit 62 and a CRT circuit 63. Here, the sound generating means for generating a sound is constituted by a sound synthesizing circuit 71, a volume amplifying circuit 72 and a speaker.

The basic circuit 53 includes a ROM 54 for storing a game control program and the like, a RAM 55 used as a work memory, a CPU 56 for performing a control operation in accordance with the control program, and an I / O port unit 57.

Further, the main board 31 is provided with an initial reset circuit 65 for resetting the CPU 56 of the basic circuit 53 when the power is turned on, and a reset pulse is given to the CPU 56 of the basic circuit 53 periodically (for example, every 2 ms). A periodic reset circuit 66 for re-executing the game control program from the beginning and an address signal provided from the basic circuit 53 are decoded to select any one of the I / O ports 57 in the I / O port unit 57. And an address decode circuit 67 for outputting a signal for the same.

FIG. 5 shows a power supply circuit 90 (not shown in FIG. 4) on the main board 31 shown in FIG.
56 and an output port 57 of the I / O port unit 57
1 to 577, the initial reset circuit 65 and the delay circuit 9
FIG. 5 is a circuit diagram shown together with No. 5 (not shown in FIG. 4). The power supply circuit 90 receives a 24V voltage and generates a 5V voltage to be supplied to each circuit on the main board 31. In this example, the initial reset circuit 65 includes a reset IC 65
It has a resistor 652 connected between the 1,5V power supply and the reset IC 651, and a capacitor 653 connected between the reset IC 651 and ground. In this example, the delay circuit 94 includes two Schmitt trigger inversion circuits 941 and 942. Schmitt trigger inversion circuits (hereinafter simply referred to as inversion circuits) 941 and 94
2, for example, C-MOSIC of model number 74HC14
Is used.

FIG. 6 is a circuit diagram showing a configuration example of the address decode circuit 67 on the main board 31 shown in FIG. In this example, the address decode circuit 67
It is composed of three decoders 671, 672, 673.
Each of the decoders 671, 672, 673 decodes the signals input to the input terminals A0, A1, A2 according to the level of the signals input to the chip select terminals CS1, CS2, CS3, and outputs the decoding result to the output terminal Y0. To Y7. In this example, a C-MOSIC indicated by a model number 74HC138 is used as the decoders 671 and 673, and a model number 74AC138 is used as the decoder 672.
Is used. 74AC13
8 is faster than the 74HC138 and is used to output the selection signals Y01 to Y07 for selecting the output port faster.

FIG. 7 shows four output ports 571 to 571 of the I / O port unit 57 on the main board 31 shown in FIG.
574 is a circuit diagram showing 574. FIG. Also, FIG.
Also shown is a buffer circuit 570 provided between the data bus No. 6 and each of the output ports 571-574. In this example, model numbers 74AC2 are used as output ports 571 to 574.
A D flip-flop C-MOSIC indicated by 73 is used. Further, as the buffer circuit 570, a C-MOS of a bus buffer represented by the model number 74AC244 is used.
IC is used.

The output port 571 outputs a control signal from the CPU 56 to a part of the lamp / LED circuit 60 and the solenoid circuit 59 shown in FIG. Output port 57
2 outputs a control signal from the CPU 56 to a part of the lamp / LED circuit 60 and the illumination board command output circuit 62 shown in FIG. The output port 573 outputs a signal from the CPU 56 to the information output circuit 64 and the prize ball substrate input / output circuit 61 shown in FIG. Then, the output port 574 outputs command data for display control to the CRT circuit 63 shown in FIG.

FIG. 8 shows another three output ports 57 of the I / O port section 57 on the main board 31 shown in FIG.
It is a circuit diagram which shows 5-577. The buffer circuit 570 shown in FIG. 8 is the same as that shown in FIG. The output ports 575, 576 respectively output control signals from the CPU 56 to a part of the lamp / LED circuit 60 shown in FIG. The output port 577 outputs a control signal from the CPU 56 to the speech synthesis circuit 71 shown in FIG.

Next, the operation will be described. FIG. 9 is a flowchart showing the operation of the basic circuit 53 on the main board 31. As described above, this process is started, for example, every 2 ms by the reset pulse generated by the periodic reset circuit 66. When the basic circuit 53 is activated,
First, the CPU 56 performs a stack setting process for setting the designated address of the stack pointer (step S1). Next, initialization processing is performed (step S
2). In the initialization processing, the CPU 56 determines whether or not the RAM 55 contains an error, and if an error is included, performs processing such as initializing the RAM 55. Then, the command code transmitted to the image display unit 9 is
After performing the process of setting a predetermined area of M55 (step S3), the process of outputting a command code via the output port 574 is performed (step S4).

Next, the LED is applied to the illumination board 35 via the output port 572 and the illumination board command output circuit 62.
In addition to performing processing for transmitting a predetermined command for lighting control, the output port 573 and the information output circuit 64
Jackpot information on the computer for hall management via
A process for transmitting data such as start information and probability variation information is performed (data output process: step S5). Also,
Various abnormality diagnosis processing is performed by a self-diagnosis function provided inside the pachinko gaming machine 1, and an alarm is issued if necessary according to the result (error processing: step S6).

Next, a process for updating each counter indicating each random number for determination is performed (step S7). In step S7, the CPU 56 counts up (addition of 1) the jackpot determination random number for determining whether or not to make a jackpot and the specific symbol determination random number for determining the combination of symbols at the time of the jackpot. That is, they are the random numbers for determination.

Next, the CPU 56 performs a special symbol process (step S8). In the special symbol process control, a corresponding process is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to a gaming state. Then, the value of the special symbol process flag is updated during each processing according to the gaming state. In the special symbol process, the CPU
56 outputs a control signal to the solenoids 16 and 21 at a predetermined timing via the output port 571 and the solenoid circuit 59, and gives a control signal according to the progress of the game to the voice synthesis circuit 71 via the output port 577.

The CPU 56 performs a normal symbol process (step S9). In the normal symbol process process, a corresponding process is selected and executed according to a normal symbol process flag for controlling the variable display 10 using the 7-segment LED in a predetermined order. Then, the value of the normal symbol process flag is updated during each process according to the gaming state. Further, the CPU 56 controls the switch circuit 5
The state of the gate sensor 12, the starting port sensor 17, the count sensor 23, and the V count sensor 22 are input through the input port 8 and the input port, and it is determined whether or not there is a prize for each prize port or prize ball device (step S10). .

The CPU 56 further performs a process of updating the display random number (step S11). That is, count-up (1 addition) of a random number for determining a missing symbol and a reach determination random number for determining whether or not to reach is performed.

The basic circuit 53 performs signal processing with the award ball substrate 37 (step S12). The winning is detected by the winning ball detector 122. In this case, the winning ball substrate 37 outputs a winning data signal. CP
When the winning data signal is input via the input port, U56 turns ON / OF each sensor confirmed in step S10.
The number of winning balls according to the F state is determined, and the determination result is output to the winning ball substrate 37 via the output port 573 and the winning ball substrate input / output circuit 61 as a winning ball number signal. Prize ball board 37
The payout control microcomputer mounted on the
The ball payout device 97 is driven according to the prize ball number signal.

After that, the basic circuit 53 repeats the display random number updating process in step S13 until a reset pulse is next given from the periodic reset circuit 66. That is, 1 is added to the value of each random number.

Next, with reference to the circuit diagrams of FIGS. 5 to 8 and the timing chart of FIG. 10, control relating to reset of the CPU 56 and the I / O port unit 57 will be described. First, the output ports 571 to 5 in the I / O port unit 57
The selection control of 77 will be described. The decoder 671 shown in FIG. 6 includes address signals A7, A6,
A5 is introduced to the chip select terminals CS1, CS2, CS3. When only the signal input to the chip select terminal CS1 is at the high level, the decoder 671 is activated, so that the address signal from the CPU 57 is (xx).
xxx100xxxxxx), the decoder 671
Becomes active. Note that (xxxxxx100xxx
xx) corresponds to the address signal A12, and the rightmost corresponds to the address signal A0. “X” is “0”
(Low level) "or" 1 (high level) ". When the decoder 671 is activated, the decoding result of the read / write signal R / W # and the address signals A3, A4 from the CPU 56 input to the input terminals A0, A1, A2 is output to the output terminals Y0 to Y7. Read / write signal R / W # is a signal that goes low when CPU 56 outputs data. Output terminal Y0
All signals input to the input terminals A0, A1, A2 are 0
Since a low level which is a significant level is output at the time of (low level), after all, when the address signal from the CPU 57 is (xxxx10000xxx) and the read / write signal R / W # is at the low level, A low level appears at the output terminal Y0.

When the address signal from the CPU 57 is (xxxxxx10000xxx) and the read / write signal R / W # is at a high level, the output terminal Y1
A low level appears. When inputting data, the CPU 56 sets the read / write signal R / W # to high level.

The decoder 672 has output ports 571-5
The selection signals Y01 to Y07 for selecting 77 are generated. In the decoder 672, an E clock output from the CPU 56, a Y0 output of the decoder 671,
IO select signal CSIO0 output from CPU 56
￣ has been entered. And the chip select terminal CS
1 is at a high level and the signals input to the chip select terminals CS2 and CS3 are at a low level, the decoder 672 becomes active, and the address signals input to the input terminals A0, A1 and A2. A0, A
1, A2, and outputs the decoded results to output terminals Y0 to Y0.
Output to Y7. That is, when the E clock is at a high level and the Y0 output of decoder 671 and IO select signal CSIO0 # are at a low level, Y0 to Y
Any of the seven outputs goes to a low level, which is a significant level.

For convenience, input terminals A0, A1, A2
Although the same reference numerals are used as in the case of the address signals A0, A1, A2, the input terminals A0, A1, A2 and the address signals A0, A1, A2 have different concepts. The E clock is a clock that is output by the CPU 56 in order to synchronize with peripheral circuits. The IO select signal CSIO0 # is set to a low level when the CPU 56 specifies an address of 20xx in hexadecimal (00100000xxxxxxx in binary). Signal.

When the decoder 672 is active, the Y0 output of the decoder 671 is at a low level. The Y0 output of the decoder 671 becomes low level when the address signal from the CPU 57 is (xxxxx).
10000xxx). Also, the decoder 67
2 is active, IO select signal CSIO0 # is at a low level. When IO select signal CSIO0 # is at a low level,
The CPU 56 specifies (00100000xxxxxxxxx). Therefore, the CPU 56 sets (0010000
010000xxx), that is, when an I / O output instruction designating the 2080 address block in hexadecimal is executed, the decoder 67
2, one of the Y0 to Y7 outputs goes low.

Which one of the outputs Y0 to Y7 is set to the low level depends on the input terminals A0, A1, A2 of the decoder 672.
Is determined by the levels of the address signals A0, A1, and A2 input to the first and second terminals. For example, address signals A0, A1, A2 =
When 0, 0, 0 (all low levels), the Y0 output goes low, and the address signals A0, A1, A2 = 1,
When it is 0,0, the Y1 output goes low.

The selection signals Y01 to Y07 are the outputs of Y1 to Y7 of the decoder 672, respectively.
The address specified by U56 and the timing when the selection signals Y01 to Y07 go low have the following relationship. Y01 ... 2081 (H) Y02 ... 2082 (H) Y03 ... 2083 (H) Y04 ... 2084 (H) Y05 ... 2085 (H) Y06 ... 2086 (H) Y07. 2087 (H) (H) means hexadecimal.

Similarly, a decoder 673 that generates a selection signal Y10 for selecting an input port (not shown)
I / O that the CPU 56 specifies the address of 2080 (H)
When the O input instruction is executed, the level becomes low.

The data output from the CPU 56 to the data bus is output from the buffer circuit 570 as data WR0 to WR7 with a slight delay inside the buffer circuit 570. Each of the output ports 571 to 577 is configured by a D flip-flop, and the selection signals Y01 to Y07 are input to the clock input terminals of each of the output ports 571 to 577. Further, data WR0 to WR from the buffer circuit 570 are input to the output ports 571 to 577 as data inputs.
7 has been entered. Therefore, the selection signals Y01 to Y07
At the time of the rising edge of the data, the data WR0 to WR7 are latched by the output ports 571 to 577, and the output ports 571 to 57
7 is output. The selection signals Y01 to Y07 are supplied to the CPU 5
6 becomes low level when the addresses 2081 (H) to 2087 (H) are specified, so that when the CPU 56 specifies the addresses 2081 (H) to 2087 (H), the signals on the data bus are Output port 571 to
577. The output ports 571 to 57
7 is composed of flip-flops, so that data is output to output ports 571 to 57 until the next address is specified.
7 is held.

Next, the reset control at the time of turning on the power will be described. When the power of the gaming machine is turned on, the power supply circuit 90 shown in FIG.
Start supplying to each circuit in. The power supply circuit 90 also generates a 24V voltage for driving a solenoid or the like and a 12V voltage used in the volume amplification circuit 72 and the like. In the initial reset circuit 65, when a 5V voltage is applied, the capacitor 653 is charged, and the resistor 652 and the capacitor 65
3, that is, the input voltage of the reset IC gradually increases. Then, when the input voltage of the reset IC exceeds a predetermined value, the output of the reset IC changes from a low level to a high level. The output of the reset IC is the CPU 56
Connected to the reset terminal. Therefore, FIG.
As shown in (A) CPU reset, the potential of the reset terminal of the CPU 56 becomes high level a little after the 5V voltage is applied to the main board 31 (when the output of the reset IC becomes high level). The CPU 56 is released from the reset state and is ready for operation.

The output of the reset IC is also input to the delay circuit 94. In the delay circuit 94, the input signal is output from the delay circuit 94 with a delay of the signal delay time of the two inversion circuits 941 and 942. The output of the delay circuit 94 is input to the reset terminals of the output ports 571 to 577. Therefore, I / in FIG.
As shown by O reset, each output port 571-577
The potential of the reset terminal becomes high level with a delay of the signal delay time in the delay circuit 94 after the reset of the CPU 56 is released. Each output port 571-57
7 does not operate during a period when the potential of the reset terminal is at a low level, and outputs an inactive output level from each output terminal. Then, when the potential of the reset terminal goes to a high level, the reset state is released and the device becomes operable.

When the output ports 571 to 577 become operable, the signals on the data bus via the buffer circuit 570 are output at the rising timing of the selection signals Y01 to Y07 output from the decoder 672 shown in FIG. Capture and output it.

FIG. 10B is a timing chart showing a case where the reset release timing of the CPU 56 and the reset release timing of each of the output ports 571 to 577 are simultaneous. Such a timing relationship is obtained by, for example, outputting the output of the initial reset circuit 65 to the CPU 56 and the output port 5.
This can occur when connected to reset terminals 71-577. FIG. 10C is a timing chart showing a case where the reset release timing of the CPU 56 is earlier than the reset release timing of each of the output ports 571 to 577. Such a timing relationship is determined by, for example, the output ports 571 to 57 regardless of the output of the initial reset circuit 65.
7 can occur when the reset release timing is created.

When the timing relationship as shown in FIG. 10C occurs, there is a possibility that incorrect data is output from the output ports 571 to 577 as shown in FIG. The signals on the data bus and the address bus are not fixed until the reset of the CPU 56 is released after the gaming machine is turned on. Then, noise or the like at power-on may appear on the data bus and the address bus. In this example, the output ports 571 to 577 are configured by D flip-flops, and a clock terminal receives a signal obtained by decoding an address signal. Therefore, a rising signal due to noise on the address bus may be input to the clock terminals of the output ports 571 to 577. As shown in FIG.
If the 577 becomes operable earlier, the output ports 571 to 577 may capture a signal on the data bus that has not been determined due to a clock terminal input caused by noise. In such a case, output port 5
Incorrect data will be output from 71 to 577.

The CPU 56 as shown in FIG.
Reset release timing and output ports 571-57
7, the operation of the output ports 571 to 577 may be started earlier due to variations in elements. In such a case, there is a possibility that the signals on the data bus whose output ports 571 to 577 have not been determined may be fetched.

Therefore, if no consideration is given between the reset release timing of the CPU 56 and the reset release timing of the output ports 571 to 577, the solenoid circuit 59, the lamp / LED circuit 60, the prize ball board input / output circuit 61 , Illumination board command output circuit 62, CRT circuit 6
3. Incorrect data may be output to the information output circuit 64 and the speech synthesis circuit 71 when the power is turned on. Solenoid circuit 59, lamp / LED circuit 6
0, the output of the winning ball substrate input / output circuit 61, the illumination board command output circuit 62, the CRT circuit 63, the information output circuit 64, and the voice synthesis circuit 71 are output from the variable winning ball device 15 and the solenoid 16, which opens the opening / closing plate 20, 21, display 10,
18, decorative lamp 25, prize ball board 37, illumination board 35,
Since they are provided to the CRT circuit 63, the hall computer, and the speaker, they may be illegally driven.

When the CPU 56 starts operating, if a program is first set to clear the outputs of the output ports 571 to 577, the illegal data from the output ports 571 to 577 is cleared in a short period of time. However, even in such a case, signals to the boards other than the main board 31 and signals to other devices outside the game machine, which are output through the output ports 571 to 577, are not transmitted to other boards or other devices. There is a possibility that it will be captured in the device. That is,
There is a possibility that the illegal data output for a short time is transmitted to another substrate or device and accepted by another substrate or device. Some measures must be taken on other substrates or devices to eliminate such possibilities, but such measures are generally complex.

However, in this embodiment, since the operation start time of the output ports 571 to 577 is always later than the operation start time of the CPU 56, there is no possibility that the output ports 571 to 577 output illegal data. As described above, the output of the initial reset circuit 65 that supplies the CPU 56 with the reset signal at the time of power-on is delayed so that each output port 5
Since the input is made to the reset terminals 71 to 577, it is possible to reliably prevent the output data from being output from the output ports 571 to 577 when the power is turned on.

In the above embodiment, an example in which two inverting circuits 941 and 942 are used as the delay circuit 94 has been described, but the configuration of the delay circuit 94 is not limited to such a configuration. For example, as shown in FIG.
A delay circuit 94A in which a capacitor 943 is inserted between 1,942 may be used. Also, as shown in FIG.
A delay circuit 94B in which a capacitor 943 and a resistor 944 are inserted between two inversion circuits 941 and 942 may be used. In the configuration shown in FIG. 11, a delay time due to the product of the output resistance value of the inverting circuit 941 and the capacitance of the capacitor 943 can be ensured. In the configuration shown in FIG. 12, the resistance value of the resistor 944 and the capacitance of the capacitor 943 are provided. , And a delay time can be secured. Therefore, a delay time longer than the delay time by the delay circuit 94 shown in FIG. 5 can be secured, and the output of illegal data can be prevented more reliably.

In the above embodiment, the case where the image display unit 9 using a CRT for variably displaying symbols is used has been described, but the case where a variable display device using an LCD is used may be used. Furthermore, the present invention can also be applied to video-type pachinko game machines and slot machines in which the entire board is composed of video.

[0053]

As described above, according to the present invention, the gaming machine is configured to release the reset of the interface means after a predetermined period from the release of the reset of the control means.
This has the effect of reliably preventing illegal data from being output from the interface means when the power is turned on. When the reset unit has a configuration including a control reset unit that resets the control unit and a delay unit that delays the output of the control reset unit and provides the output to the interface unit, only one reset unit is provided. The reset release timing of the interface means can be delayed from the reset release timing of the control means. When the interface means is configured to output a control signal to at least a solenoid circuit for driving the variable prize ball device, a display drive circuit for driving the display and the lighting element, and a sound generating means for generating sound. The game is started with the variable winning prize device open, the game is started with a specific display on the display, the lighting element and the sound generation means are abnormally lit, and an abnormal sound is generated. Is reliably prevented.

[Brief description of the drawings]

FIG. 1 is a front view of a pachinko gaming machine viewed from the front.

FIG. 2 is an overall rear view showing the internal structure of the pachinko gaming machine.

FIG. 3 is a rear view of the gaming board of the pachinko gaming machine as viewed from the rear.

FIG. 4 is a block diagram showing an example of a circuit configuration in the game control board.

FIG. 5 is a circuit diagram showing a power supply circuit, a CPU, and an output port on a main board together with an initial reset circuit and a delay circuit.

FIG. 6 is a circuit diagram illustrating a configuration example of an address decode circuit.

FIG. 7 is a circuit diagram showing four output ports of the I / O port unit.

FIG. 8 is a circuit diagram showing another three output ports of the I / O port unit.

FIG. 9 is a flowchart showing the operation of the basic circuit.

FIG. 10 is a timing chart showing reset release timings of a CPU and an output port.

FIG. 11 is a circuit diagram showing another configuration of the delay circuit.

FIG. 12 is a circuit diagram showing still another configuration of the delay circuit.

[Explanation of symbols]

 31 Game control board 53 Basic circuit 56 CPU 57 I / O port section 571-577 Output port 65 Initial reset circuit 94, 94A, 94B Delay circuit

Claims (3)

[Claims] 1. A game machine, comprising: a specific winning port in which a game ball can be awarded; and a special gaming device for performing a predetermined special game when a gaming ball wins in the specific winning port, is provided on a game board. In a gaming machine capable of providing a game value to a player based on a result, a control means for controlling the progress of a game, a plurality of interface means for taking in and outputting a control signal from the control means, A gaming machine comprising: reset means for resetting the interface means and canceling the reset of the interface means after a predetermined period from the reset release of the control means. 2. The gaming machine according to claim 1, wherein the reset means includes a control reset means for resetting the control means, and a delay means for delaying the output of the control reset means and providing the output to the interface means. 3. An interface means for outputting a control signal to at least a solenoid circuit for driving a variable winning ball device, a display drive circuit for driving a display and a lighting element, and a sound generating means for generating sound. A gaming machine according to claim 1 or claim 2.